riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   state.dcsr.cause = cause;
 193   state.dcsr.prv = state.prv;
 194   set_privilege(PRV_M);
 195   state.dpc = state.pc;
 196   state.pc = DEBUG_ROM_START;
 197 }
 198
 199 void processor_t::take_trap(trap_t& t, reg_t epc)
 200 {
 201   if (debug) {
 202     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 203             id, t.name(), epc);
 204     if (t.has_badaddr())
 205       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 206           t.get_badaddr());
 207   }
 208
 209   if (t.cause() == CAUSE_BREAKPOINT && (
 210               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 211               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 212               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 213               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 214     enter_debug_mode(DCSR_CAUSE_SWBP);
 215     return;
 216   }
 217
 218   if (state.dcsr.cause) {
 219     state.pc = DEBUG_ROM_EXCEPTION;
 220     return;
 221   }
 222
 223   // by default, trap to M-mode, unless delegated to S-mode
 224   reg_t bit = t.cause();
 225   reg_t deleg = state.medeleg;
 226   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 227   if (interrupt)
 228     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 229   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 230     // handle the trap in S-mode
 231     state.pc = state.stvec;
 232     state.scause = t.cause();
 233     state.sepc = epc;
 234     if (t.has_badaddr())
 235       state.sbadaddr = t.get_badaddr();
 236
 237     reg_t s = state.mstatus;
 238     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 239     s = set_field(s, MSTATUS_SPP, state.prv);
 240     s = set_field(s, MSTATUS_SIE, 0);
 241     set_csr(CSR_MSTATUS, s);
 242     set_privilege(PRV_S);
 243   } else {
 244     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 245     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 246     state.mepc = epc;
 247     state.mcause = t.cause();
 248     if (t.has_badaddr())
 249       state.mbadaddr = t.get_badaddr();
 250
 251     reg_t s = state.mstatus;
 252     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 253     s = set_field(s, MSTATUS_MPP, state.prv);
 254     s = set_field(s, MSTATUS_MIE, 0);
 255     set_csr(CSR_MSTATUS, s);
 256     set_privilege(PRV_M);
 257   }
 258
 259   yield_load_reservation();
 260 }
 261
 262 void processor_t::disasm(insn_t insn)
 263 {
 264   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 265   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 266           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 267 }
 268
 269 int processor_t::paddr_bits()
 270 {
 271   assert(xlen == max_xlen);
 272   return max_xlen == 64 ? 50 : 34;
 273 }
 274
 275 void processor_t::set_csr(int which, reg_t val)
 276 {
 277   val = zext_xlen(val);
 278   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 279   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 280   switch (which)
 281   {
 282     case CSR_FFLAGS:
 283       dirty_fp_state;
 284       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 285       break;
 286     case CSR_FRM:
 287       dirty_fp_state;
 288       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 289       break;
 290     case CSR_FCSR:
 291       dirty_fp_state;
 292       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 293       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 294       break;
 295     case CSR_MSTATUS: {
 296       if ((val ^ state.mstatus) &
 297           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 298         mmu->flush_tlb();
 299
 300       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 301                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 302                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 303                  | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
 304
 305       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 306
 307       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 308       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 309       if (max_xlen == 32)
 310         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 311       else
 312         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 313
 314       // spike supports the notion of xlen < max_xlen, but current priv spec
 315       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 316       xlen = max_xlen;
 317       break;
 318     }
 319     case CSR_MIP: {
 320       reg_t mask = MIP_SSIP | MIP_STIP;
 321       state.mip = (state.mip & ~mask) | (val & mask);
 322       break;
 323     }
 324     case CSR_MIE:
 325       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 326       break;
 327     case CSR_MIDELEG:
 328       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 329       break;
 330     case CSR_MEDELEG: {
 331       reg_t mask = 0;
 332 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 333 #include "encoding.h"
 334 #undef DECLARE_CAUSE
 335       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 336       break;
 337     }
 338     case CSR_MINSTRET:
 339     case CSR_MCYCLE:
 340       if (xlen == 32)
 341         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 342       else
 343         state.minstret = val;
 344       break;
 345     case CSR_MINSTRETH:
 346     case CSR_MCYCLEH:
 347       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 348       break;
 349     case CSR_SCOUNTEREN:
 350       state.scounteren = val;
 351       break;
 352     case CSR_MCOUNTEREN:
 353       state.mcounteren = val;
 354       break;
 355     case CSR_SSTATUS: {
 356       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 357                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 358       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 359     }
 360     case CSR_SIP: {
 361       reg_t mask = MIP_SSIP & state.mideleg;
 362       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 363     }
 364     case CSR_SIE:
 365       return set_csr(CSR_MIE,
 366                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 367     case CSR_SPTBR: {
 368       mmu->flush_tlb();
 369       if (max_xlen == 32)
 370         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 371       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 372                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 373                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 374         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 375       break;
 376     }
 377     case CSR_SEPC: state.sepc = val; break;
 378     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 379     case CSR_SSCRATCH: state.sscratch = val; break;
 380     case CSR_SCAUSE: state.scause = val; break;
 381     case CSR_SBADADDR: state.sbadaddr = val; break;
 382     case CSR_MEPC: state.mepc = val; break;
 383     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 384     case CSR_MSCRATCH: state.mscratch = val; break;
 385     case CSR_MCAUSE: state.mcause = val; break;
 386     case CSR_MBADADDR: state.mbadaddr = val; break;
 387     case CSR_MISA: {
 388       if (!(val & (1L << ('F' - 'A'))))
 389         val &= ~(1L << ('D' - 'A'));
 390
 391       // allow MAFDC bits in MISA to be modified
 392       reg_t mask = 0;
 393       mask |= 1L << ('M' - 'A');
 394       mask |= 1L << ('A' - 'A');
 395       mask |= 1L << ('F' - 'A');
 396       mask |= 1L << ('D' - 'A');
 397       mask |= 1L << ('C' - 'A');
 398       mask &= max_isa;
 399
 400       isa = (val & mask) | (isa & ~mask);
 401       break;
 402     }
 403     case CSR_TSELECT:
 404       if (val < state.num_triggers) {
 405         state.tselect = val;
 406       }
 407       break;
 408     case CSR_TDATA1:
 409       {
 410         mcontrol_t *mc = &state.mcontrol[state.tselect];
 411         if (mc->dmode && !state.dcsr.cause) {
 412           break;
 413         }
 414         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 415         mc->select = get_field(val, MCONTROL_SELECT);
 416         mc->timing = get_field(val, MCONTROL_TIMING);
 417         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 418         mc->chain = get_field(val, MCONTROL_CHAIN);
 419         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 420         mc->m = get_field(val, MCONTROL_M);
 421         mc->h = get_field(val, MCONTROL_H);
 422         mc->s = get_field(val, MCONTROL_S);
 423         mc->u = get_field(val, MCONTROL_U);
 424         mc->execute = get_field(val, MCONTROL_EXECUTE);
 425         mc->store = get_field(val, MCONTROL_STORE);
 426         mc->load = get_field(val, MCONTROL_LOAD);
 427         // Assume we're here because of csrw.
 428         if (mc->execute)
 429           mc->timing = 0;
 430         trigger_updated();
 431       }
 432       break;
 433     case CSR_TDATA2:
 434       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 435         break;
 436       }
 437       if (state.tselect < state.num_triggers) {
 438         state.tdata2[state.tselect] = val;
 439       }
 440       break;
 441     case CSR_DCSR:
 442       state.dcsr.prv = get_field(val, DCSR_PRV);
 443       state.dcsr.step = get_field(val, DCSR_STEP);
 444       // TODO: ndreset and fullreset
 445       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 446       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 447       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 448       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 449       state.dcsr.halt = get_field(val, DCSR_HALT);
 450       break;
 451     case CSR_DPC:
 452       state.dpc = val;
 453       break;
 454     case CSR_DSCRATCH:
 455       state.dscratch = val;
 456       break;
 457   }
 458 }
 459
 460 reg_t processor_t::get_csr(int which)
 461 {
 462   uint32_t ctr_en = -1;
 463   if (state.prv < PRV_M)
 464     ctr_en &= state.mcounteren;
 465   if (state.prv < PRV_S)
 466     ctr_en &= state.scounteren;
 467   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 468
 469   if (ctr_ok) {
 470     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 471       return 0;
 472     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 473       return 0;
 474   }
 475   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 476     return 0;
 477   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 478     return 0;
 479   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 480     return 0;
 481
 482   switch (which)
 483   {
 484     case CSR_FFLAGS:
 485       require_fp;
 486       if (!supports_extension('F'))
 487         break;
 488       return state.fflags;
 489     case CSR_FRM:
 490       require_fp;
 491       if (!supports_extension('F'))
 492         break;
 493       return state.frm;
 494     case CSR_FCSR:
 495       require_fp;
 496       if (!supports_extension('F'))
 497         break;
 498       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 499     case CSR_INSTRET:
 500     case CSR_CYCLE:
 501       if (ctr_ok)
 502         return state.minstret;
 503       break;
 504     case CSR_MINSTRET:
 505     case CSR_MCYCLE:
 506       return state.minstret;
 507     case CSR_MINSTRETH:
 508     case CSR_MCYCLEH:
 509       if (xlen == 32)
 510         return state.minstret >> 32;
 511       break;
 512     case CSR_SCOUNTEREN: return state.scounteren;
 513     case CSR_MCOUNTEREN: return state.mcounteren;
 514     case CSR_SSTATUS: {
 515       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 516                  | SSTATUS_XS | SSTATUS_SUM;
 517       reg_t sstatus = state.mstatus & mask;
 518       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 519           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 520         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 521       return sstatus;
 522     }
 523     case CSR_SIP: return state.mip & state.mideleg;
 524     case CSR_SIE: return state.mie & state.mideleg;
 525     case CSR_SEPC: return state.sepc;
 526     case CSR_SBADADDR: return state.sbadaddr;
 527     case CSR_STVEC: return state.stvec;
 528     case CSR_SCAUSE:
 529       if (max_xlen > xlen)
 530         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 531       return state.scause;
 532     case CSR_SPTBR:
 533       if (get_field(state.mstatus, MSTATUS_TVM))
 534         require_privilege(PRV_M);
 535       return state.sptbr;
 536     case CSR_SSCRATCH: return state.sscratch;
 537     case CSR_MSTATUS: return state.mstatus;
 538     case CSR_MIP: return state.mip;
 539     case CSR_MIE: return state.mie;
 540     case CSR_MEPC: return state.mepc;
 541     case CSR_MSCRATCH: return state.mscratch;
 542     case CSR_MCAUSE: return state.mcause;
 543     case CSR_MBADADDR: return state.mbadaddr;
 544     case CSR_MISA: return isa;
 545     case CSR_MARCHID: return 0;
 546     case CSR_MIMPID: return 0;
 547     case CSR_MVENDORID: return 0;
 548     case CSR_MHARTID: return id;
 549     case CSR_MTVEC: return state.mtvec;
 550     case CSR_MEDELEG: return state.medeleg;
 551     case CSR_MIDELEG: return state.mideleg;
 552     case CSR_TSELECT: return state.tselect;
 553     case CSR_TDATA1:
 554       if (state.tselect < state.num_triggers) {
 555         reg_t v = 0;
 556         mcontrol_t *mc = &state.mcontrol[state.tselect];
 557         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 558         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 559         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 560         v = set_field(v, MCONTROL_SELECT, mc->select);
 561         v = set_field(v, MCONTROL_TIMING, mc->timing);
 562         v = set_field(v, MCONTROL_ACTION, mc->action);
 563         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 564         v = set_field(v, MCONTROL_MATCH, mc->match);
 565         v = set_field(v, MCONTROL_M, mc->m);
 566         v = set_field(v, MCONTROL_H, mc->h);
 567         v = set_field(v, MCONTROL_S, mc->s);
 568         v = set_field(v, MCONTROL_U, mc->u);
 569         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 570         v = set_field(v, MCONTROL_STORE, mc->store);
 571         v = set_field(v, MCONTROL_LOAD, mc->load);
 572         return v;
 573       } else {
 574         return 0;
 575       }
 576       break;
 577     case CSR_TDATA2:
 578       if (state.tselect < state.num_triggers) {
 579         return state.tdata2[state.tselect];
 580       } else {
 581         return 0;
 582       }
 583       break;
 584     case CSR_TDATA3: return 0;
 585     case CSR_DCSR:
 586       {
 587         uint32_t v = 0;
 588         v = set_field(v, DCSR_XDEBUGVER, 1);
 589         v = set_field(v, DCSR_NDRESET, 0);
 590         v = set_field(v, DCSR_FULLRESET, 0);
 591         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 592         v = set_field(v, DCSR_STEP, state.dcsr.step);
 593         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 594         v = set_field(v, DCSR_STOPCYCLE, 0);
 595         v = set_field(v, DCSR_STOPTIME, 0);
 596         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 597         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 598         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 599         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 600         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 601         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 602         return v;
 603       }
 604     case CSR_DPC:
 605       return state.dpc;
 606     case CSR_DSCRATCH:
 607       return state.dscratch;
 608   }
 609   throw trap_illegal_instruction(0);
 610 }
 611
 612 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 613 {
 614   throw trap_illegal_instruction(0);
 615 }
 616
 617 insn_func_t processor_t::decode_insn(insn_t insn)
 618 {
 619   // look up opcode in hash table
 620   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 621   insn_desc_t desc = opcode_cache[idx];
 622
 623   if (unlikely(insn.bits() != desc.match)) {
 624     // fall back to linear search
 625     insn_desc_t* p = &instructions[0];
 626     while ((insn.bits() & p->mask) != p->match)
 627       p++;
 628     desc = *p;
 629
 630     if (p->mask != 0 && p > &instructions[0]) {
 631       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 632         // move to front of opcode list to reduce miss penalty
 633         while (--p >= &instructions[0])
 634           *(p+1) = *p;
 635         instructions[0] = desc;
 636       }
 637     }
 638
 639     opcode_cache[idx] = desc;
 640     opcode_cache[idx].match = insn.bits();
 641   }
 642
 643   return xlen == 64 ? desc.rv64 : desc.rv32;
 644 }
 645
 646 void processor_t::register_insn(insn_desc_t desc)
 647 {
 648   instructions.push_back(desc);
 649 }
 650
 651 void processor_t::build_opcode_map()
 652 {
 653   struct cmp {
 654     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 655       if (lhs.match == rhs.match)
 656         return lhs.mask > rhs.mask;
 657       return lhs.match > rhs.match;
 658     }
 659   };
 660   std::sort(instructions.begin(), instructions.end(), cmp());
 661
 662   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 663     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 664 }
 665
 666 void processor_t::register_extension(extension_t* x)
 667 {
 668   for (auto insn : x->get_instructions())
 669     register_insn(insn);
 670   build_opcode_map();
 671   for (auto disasm_insn : x->get_disasms())
 672     disassembler->add_insn(disasm_insn);
 673   if (ext != NULL)
 674     throw std::logic_error("only one extension may be registered");
 675   ext = x;
 676   x->set_processor(this);
 677 }
 678
 679 void processor_t::register_base_instructions()
 680 {
 681   #define DECLARE_INSN(name, match, mask) \
 682     insn_bits_t name##_match = (match), name##_mask = (mask);
 683   #include "encoding.h"
 684   #undef DECLARE_INSN
 685
 686   #define DEFINE_INSN(name) \
 687     REGISTER_INSN(this, name, name##_match, name##_mask)
 688   #include "insn_list.h"
 689   #undef DEFINE_INSN
 690
 691   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 692   build_opcode_map();
 693 }
 694
 695 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 696 {
 697   switch (addr)
 698   {
 699     case 0:
 700       if (len <= 4) {
 701         memset(bytes, 0, len);
 702         bytes[0] = get_field(state.mip, MIP_MSIP);
 703         return true;
 704       }
 705       break;
 706   }
 707
 708   return false;
 709 }
 710
 711 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 712 {
 713   switch (addr)
 714   {
 715     case 0:
 716       if (len <= 4) {
 717         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 718         return true;
 719       }
 720       break;
 721   }
 722
 723   return false;
 724 }
 725
 726 void processor_t::trigger_updated()
 727 {
 728   mmu->flush_tlb();
 729   mmu->check_triggers_fetch = false;
 730   mmu->check_triggers_load = false;
 731   mmu->check_triggers_store = false;
 732
 733   for (unsigned i = 0; i < state.num_triggers; i++) {
 734     if (state.mcontrol[i].execute) {
 735       mmu->check_triggers_fetch = true;
 736     }
 737     if (state.mcontrol[i].load) {
 738       mmu->check_triggers_load = true;
 739     }
 740     if (state.mcontrol[i].store) {
 741       mmu->check_triggers_store = true;
 742     }
 743   }
 744 }