riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   // advertise support for supervisor and user modes
 116   isa |= 1L << ('s' - 'a');
 117   isa |= 1L << ('u' - 'a');
 118
 119   max_isa = isa;
 120 }
 121
 122 void state_t::reset()
 123 {
 124   memset(this, 0, sizeof(*this));
 125   prv = PRV_M;
 126   pc = DEFAULT_RSTVEC;
 127   load_reservation = -1;
 128   tselect = 0;
 129   for (unsigned int i = 0; i < num_triggers; i++)
 130     mcontrol[i].type = 2;
 131 }
 132
 133 void processor_t::set_debug(bool value)
 134 {
 135   debug = value;
 136   if (ext)
 137     ext->set_debug(value);
 138 }
 139
 140 void processor_t::set_histogram(bool value)
 141 {
 142   histogram_enabled = value;
 143 #ifndef RISCV_ENABLE_HISTOGRAM
 144   if (value) {
 145     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 146     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 147   }
 148 #endif
 149 }
 150
 151 void processor_t::reset()
 152 {
 153   state.reset();
 154   state.dcsr.halt = halt_on_reset;
 155   halt_on_reset = false;
 156   set_csr(CSR_MSTATUS, state.mstatus);
 157
 158   if (ext)
 159     ext->reset(); // reset the extension
 160 }
 161
 162 // Count number of contiguous 0 bits starting from the LSB.
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt(reg_t pending_interrupts)
 173 {
 174   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 175   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 176   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 177
 178   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 179   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 180   if (enabled_interrupts == 0)
 181     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (state.dcsr.cause == 0 && enabled_interrupts)
 184     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 185 }
 186
 187 static int xlen_to_uxl(int xlen)
 188 {
 189   if (xlen == 32)
 190     return 1;
 191   if (xlen == 64)
 192     return 2;
 193   abort();
 194 }
 195
 196 void processor_t::set_privilege(reg_t prv)
 197 {
 198   assert(prv <= PRV_M);
 199   if (prv == PRV_H)
 200     prv = PRV_U;
 201   mmu->flush_tlb();
 202   state.prv = prv;
 203 }
 204
 205 void processor_t::enter_debug_mode(uint8_t cause)
 206 {
 207   state.dcsr.cause = cause;
 208   state.dcsr.prv = state.prv;
 209   set_privilege(PRV_M);
 210   state.dpc = state.pc;
 211   state.pc = DEBUG_ROM_ENTRY;
 212 }
 213
 214 void processor_t::take_trap(trap_t& t, reg_t epc)
 215 {
 216   if (debug) {
 217     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 218             id, t.name(), epc);
 219     if (t.has_badaddr())
 220       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 221           t.get_badaddr());
 222   }
 223
 224   if (state.dcsr.cause) {
 225     if (t.cause() == CAUSE_BREAKPOINT) {
 226       state.pc = DEBUG_ROM_ENTRY;
 227     } else {
 228       state.pc = DEBUG_ROM_TVEC;
 229     }
 230     return;
 231   }
 232
 233   if (t.cause() == CAUSE_BREAKPOINT && (
 234               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 235               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 236               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 237               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 238     enter_debug_mode(DCSR_CAUSE_SWBP);
 239     return;
 240   }
 241
 242   // by default, trap to M-mode, unless delegated to S-mode
 243   reg_t bit = t.cause();
 244   reg_t deleg = state.medeleg;
 245   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 246   if (interrupt)
 247     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 248   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 249     // handle the trap in S-mode
 250     state.pc = state.stvec;
 251     state.scause = t.cause();
 252     state.sepc = epc;
 253     if (t.has_badaddr())
 254       state.sbadaddr = t.get_badaddr();
 255
 256     reg_t s = state.mstatus;
 257     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 258     s = set_field(s, MSTATUS_SPP, state.prv);
 259     s = set_field(s, MSTATUS_SIE, 0);
 260     set_csr(CSR_MSTATUS, s);
 261     set_privilege(PRV_S);
 262   } else {
 263     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 264     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 265     state.mepc = epc;
 266     state.mcause = t.cause();
 267     if (t.has_badaddr())
 268       state.mbadaddr = t.get_badaddr();
 269
 270     reg_t s = state.mstatus;
 271     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 272     s = set_field(s, MSTATUS_MPP, state.prv);
 273     s = set_field(s, MSTATUS_MIE, 0);
 274     set_csr(CSR_MSTATUS, s);
 275     set_privilege(PRV_M);
 276   }
 277
 278   yield_load_reservation();
 279 }
 280
 281 void processor_t::disasm(insn_t insn)
 282 {
 283   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 284   if (last_pc != state.pc || last_bits != bits) {
 285     if (executions != 1) {
 286       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 287     }
 288
 289     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 290             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 291     last_pc = state.pc;
 292     last_bits = bits;
 293     executions = 1;
 294   } else {
 295     executions++;
 296   }
 297 }
 298
 299 int processor_t::paddr_bits()
 300 {
 301   assert(xlen == max_xlen);
 302   return max_xlen == 64 ? 50 : 34;
 303 }
 304
 305 void processor_t::set_csr(int which, reg_t val)
 306 {
 307   val = zext_xlen(val);
 308   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 309   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 310   switch (which)
 311   {
 312     case CSR_FFLAGS:
 313       dirty_fp_state;
 314       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 315       break;
 316     case CSR_FRM:
 317       dirty_fp_state;
 318       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 319       break;
 320     case CSR_FCSR:
 321       dirty_fp_state;
 322       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 323       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 324       break;
 325     case CSR_MSTATUS: {
 326       if ((val ^ state.mstatus) &
 327           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 328         mmu->flush_tlb();
 329
 330       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 331                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 332                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 333                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 334                  (ext ? MSTATUS_XS : 0);
 335
 336       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 337
 338       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 339       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 340       if (max_xlen == 32)
 341         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 342       else
 343         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 344
 345       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 346       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 347       // U-XLEN == S-XLEN == M-XLEN
 348       xlen = max_xlen;
 349       break;
 350     }
 351     case CSR_MIP: {
 352       reg_t mask = MIP_SSIP | MIP_STIP;
 353       state.mip = (state.mip & ~mask) | (val & mask);
 354       break;
 355     }
 356     case CSR_MIE:
 357       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 358       break;
 359     case CSR_MIDELEG:
 360       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 361       break;
 362     case CSR_MEDELEG: {
 363       reg_t mask =
 364         (1 << CAUSE_MISALIGNED_FETCH) |
 365         (1 << CAUSE_BREAKPOINT) |
 366         (1 << CAUSE_USER_ECALL) |
 367         (1 << CAUSE_FETCH_PAGE_FAULT) |
 368         (1 << CAUSE_LOAD_PAGE_FAULT) |
 369         (1 << CAUSE_STORE_PAGE_FAULT);
 370       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 371       break;
 372     }
 373     case CSR_MINSTRET:
 374     case CSR_MCYCLE:
 375       if (xlen == 32)
 376         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 377       else
 378         state.minstret = val;
 379       break;
 380     case CSR_MINSTRETH:
 381     case CSR_MCYCLEH:
 382       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 383       break;
 384     case CSR_SCOUNTEREN:
 385       state.scounteren = val;
 386       break;
 387     case CSR_MCOUNTEREN:
 388       state.mcounteren = val;
 389       break;
 390     case CSR_SSTATUS: {
 391       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 392                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 393       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 394     }
 395     case CSR_SIP: {
 396       reg_t mask = MIP_SSIP & state.mideleg;
 397       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 398     }
 399     case CSR_SIE:
 400       return set_csr(CSR_MIE,
 401                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 402     case CSR_SPTBR: {
 403       mmu->flush_tlb();
 404       if (max_xlen == 32)
 405         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 406       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 407                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 408                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 409         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 410       break;
 411     }
 412     case CSR_SEPC: state.sepc = val; break;
 413     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 414     case CSR_SSCRATCH: state.sscratch = val; break;
 415     case CSR_SCAUSE: state.scause = val; break;
 416     case CSR_SBADADDR: state.sbadaddr = val; break;
 417     case CSR_MEPC: state.mepc = val; break;
 418     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 419     case CSR_MSCRATCH: state.mscratch = val; break;
 420     case CSR_MCAUSE: state.mcause = val; break;
 421     case CSR_MBADADDR: state.mbadaddr = val; break;
 422     case CSR_MISA: {
 423       if (!(val & (1L << ('F' - 'A'))))
 424         val &= ~(1L << ('D' - 'A'));
 425
 426       // allow MAFDC bits in MISA to be modified
 427       reg_t mask = 0;
 428       mask |= 1L << ('M' - 'A');
 429       mask |= 1L << ('A' - 'A');
 430       mask |= 1L << ('F' - 'A');
 431       mask |= 1L << ('D' - 'A');
 432       mask |= 1L << ('C' - 'A');
 433       mask &= max_isa;
 434
 435       isa = (val & mask) | (isa & ~mask);
 436       break;
 437     }
 438     case CSR_TSELECT:
 439       if (val < state.num_triggers) {
 440         state.tselect = val;
 441       }
 442       break;
 443     case CSR_TDATA1:
 444       {
 445         mcontrol_t *mc = &state.mcontrol[state.tselect];
 446         if (mc->dmode && !state.dcsr.cause) {
 447           break;
 448         }
 449         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 450         mc->select = get_field(val, MCONTROL_SELECT);
 451         mc->timing = get_field(val, MCONTROL_TIMING);
 452         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 453         mc->chain = get_field(val, MCONTROL_CHAIN);
 454         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 455         mc->m = get_field(val, MCONTROL_M);
 456         mc->h = get_field(val, MCONTROL_H);
 457         mc->s = get_field(val, MCONTROL_S);
 458         mc->u = get_field(val, MCONTROL_U);
 459         mc->execute = get_field(val, MCONTROL_EXECUTE);
 460         mc->store = get_field(val, MCONTROL_STORE);
 461         mc->load = get_field(val, MCONTROL_LOAD);
 462         // Assume we're here because of csrw.
 463         if (mc->execute)
 464           mc->timing = 0;
 465         trigger_updated();
 466       }
 467       break;
 468     case CSR_TDATA2:
 469       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 470         break;
 471       }
 472       if (state.tselect < state.num_triggers) {
 473         state.tdata2[state.tselect] = val;
 474       }
 475       break;
 476     case CSR_DCSR:
 477       state.dcsr.prv = get_field(val, DCSR_PRV);
 478       state.dcsr.step = get_field(val, DCSR_STEP);
 479       // TODO: ndreset and fullreset
 480       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 481       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 482       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 483       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 484       state.dcsr.halt = get_field(val, DCSR_HALT);
 485       break;
 486     case CSR_DPC:
 487       state.dpc = val;
 488       break;
 489     case CSR_DSCRATCH:
 490       state.dscratch = val;
 491       break;
 492   }
 493 }
 494
 495 reg_t processor_t::get_csr(int which)
 496 {
 497   uint32_t ctr_en = -1;
 498   if (state.prv < PRV_M)
 499     ctr_en &= state.mcounteren;
 500   if (state.prv < PRV_S)
 501     ctr_en &= state.scounteren;
 502   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 503
 504   if (ctr_ok) {
 505     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 506       return 0;
 507     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 508       return 0;
 509   }
 510   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 511     return 0;
 512   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 513     return 0;
 514   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 515     return 0;
 516
 517   switch (which)
 518   {
 519     case CSR_FFLAGS:
 520       require_fp;
 521       if (!supports_extension('F'))
 522         break;
 523       return state.fflags;
 524     case CSR_FRM:
 525       require_fp;
 526       if (!supports_extension('F'))
 527         break;
 528       return state.frm;
 529     case CSR_FCSR:
 530       require_fp;
 531       if (!supports_extension('F'))
 532         break;
 533       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 534     case CSR_INSTRET:
 535     case CSR_CYCLE:
 536       if (ctr_ok)
 537         return state.minstret;
 538       break;
 539     case CSR_MINSTRET:
 540     case CSR_MCYCLE:
 541       return state.minstret;
 542     case CSR_MINSTRETH:
 543     case CSR_MCYCLEH:
 544       if (xlen == 32)
 545         return state.minstret >> 32;
 546       break;
 547     case CSR_SCOUNTEREN: return state.scounteren;
 548     case CSR_MCOUNTEREN: return state.mcounteren;
 549     case CSR_SSTATUS: {
 550       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 551                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 552       reg_t sstatus = state.mstatus & mask;
 553       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 554           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 555         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 556       return sstatus;
 557     }
 558     case CSR_SIP: return state.mip & state.mideleg;
 559     case CSR_SIE: return state.mie & state.mideleg;
 560     case CSR_SEPC: return state.sepc;
 561     case CSR_SBADADDR: return state.sbadaddr;
 562     case CSR_STVEC: return state.stvec;
 563     case CSR_SCAUSE:
 564       if (max_xlen > xlen)
 565         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 566       return state.scause;
 567     case CSR_SPTBR:
 568       if (get_field(state.mstatus, MSTATUS_TVM))
 569         require_privilege(PRV_M);
 570       return state.sptbr;
 571     case CSR_SSCRATCH: return state.sscratch;
 572     case CSR_MSTATUS: return state.mstatus;
 573     case CSR_MIP: return state.mip;
 574     case CSR_MIE: return state.mie;
 575     case CSR_MEPC: return state.mepc;
 576     case CSR_MSCRATCH: return state.mscratch;
 577     case CSR_MCAUSE: return state.mcause;
 578     case CSR_MBADADDR: return state.mbadaddr;
 579     case CSR_MISA: return isa;
 580     case CSR_MARCHID: return 0;
 581     case CSR_MIMPID: return 0;
 582     case CSR_MVENDORID: return 0;
 583     case CSR_MHARTID: return id;
 584     case CSR_MTVEC: return state.mtvec;
 585     case CSR_MEDELEG: return state.medeleg;
 586     case CSR_MIDELEG: return state.mideleg;
 587     case CSR_TSELECT: return state.tselect;
 588     case CSR_TDATA1:
 589       if (state.tselect < state.num_triggers) {
 590         reg_t v = 0;
 591         mcontrol_t *mc = &state.mcontrol[state.tselect];
 592         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 593         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 594         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 595         v = set_field(v, MCONTROL_SELECT, mc->select);
 596         v = set_field(v, MCONTROL_TIMING, mc->timing);
 597         v = set_field(v, MCONTROL_ACTION, mc->action);
 598         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 599         v = set_field(v, MCONTROL_MATCH, mc->match);
 600         v = set_field(v, MCONTROL_M, mc->m);
 601         v = set_field(v, MCONTROL_H, mc->h);
 602         v = set_field(v, MCONTROL_S, mc->s);
 603         v = set_field(v, MCONTROL_U, mc->u);
 604         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 605         v = set_field(v, MCONTROL_STORE, mc->store);
 606         v = set_field(v, MCONTROL_LOAD, mc->load);
 607         return v;
 608       } else {
 609         return 0;
 610       }
 611       break;
 612     case CSR_TDATA2:
 613       if (state.tselect < state.num_triggers) {
 614         return state.tdata2[state.tselect];
 615       } else {
 616         return 0;
 617       }
 618       break;
 619     case CSR_TDATA3: return 0;
 620     case CSR_DCSR:
 621       {
 622         uint32_t v = 0;
 623         v = set_field(v, DCSR_XDEBUGVER, 1);
 624         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 625         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 626         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 627         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 628         v = set_field(v, DCSR_STOPCYCLE, 0);
 629         v = set_field(v, DCSR_STOPTIME, 0);
 630         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 631         v = set_field(v, DCSR_STEP, state.dcsr.step);
 632         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 633         return v;
 634       }
 635     case CSR_DPC:
 636       return state.dpc;
 637     case CSR_DSCRATCH:
 638       return state.dscratch;
 639   }
 640   throw trap_illegal_instruction(0);
 641 }
 642
 643 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 644 {
 645   throw trap_illegal_instruction(0);
 646 }
 647
 648 insn_func_t processor_t::decode_insn(insn_t insn)
 649 {
 650   // look up opcode in hash table
 651   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 652   insn_desc_t desc = opcode_cache[idx];
 653
 654   if (unlikely(insn.bits() != desc.match)) {
 655     // fall back to linear search
 656     insn_desc_t* p = &instructions[0];
 657     while ((insn.bits() & p->mask) != p->match)
 658       p++;
 659     desc = *p;
 660
 661     if (p->mask != 0 && p > &instructions[0]) {
 662       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 663         // move to front of opcode list to reduce miss penalty
 664         while (--p >= &instructions[0])
 665           *(p+1) = *p;
 666         instructions[0] = desc;
 667       }
 668     }
 669
 670     opcode_cache[idx] = desc;
 671     opcode_cache[idx].match = insn.bits();
 672   }
 673
 674   return xlen == 64 ? desc.rv64 : desc.rv32;
 675 }
 676
 677 void processor_t::register_insn(insn_desc_t desc)
 678 {
 679   instructions.push_back(desc);
 680 }
 681
 682 void processor_t::build_opcode_map()
 683 {
 684   struct cmp {
 685     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 686       if (lhs.match == rhs.match)
 687         return lhs.mask > rhs.mask;
 688       return lhs.match > rhs.match;
 689     }
 690   };
 691   std::sort(instructions.begin(), instructions.end(), cmp());
 692
 693   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 694     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 695 }
 696
 697 void processor_t::register_extension(extension_t* x)
 698 {
 699   for (auto insn : x->get_instructions())
 700     register_insn(insn);
 701   build_opcode_map();
 702   for (auto disasm_insn : x->get_disasms())
 703     disassembler->add_insn(disasm_insn);
 704   if (ext != NULL)
 705     throw std::logic_error("only one extension may be registered");
 706   ext = x;
 707   x->set_processor(this);
 708 }
 709
 710 void processor_t::register_base_instructions()
 711 {
 712   #define DECLARE_INSN(name, match, mask) \
 713     insn_bits_t name##_match = (match), name##_mask = (mask);
 714   #include "encoding.h"
 715   #undef DECLARE_INSN
 716
 717   #define DEFINE_INSN(name) \
 718     REGISTER_INSN(this, name, name##_match, name##_mask)
 719   #include "insn_list.h"
 720   #undef DEFINE_INSN
 721
 722   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 723   build_opcode_map();
 724 }
 725
 726 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 727 {
 728   switch (addr)
 729   {
 730     case 0:
 731       if (len <= 4) {
 732         memset(bytes, 0, len);
 733         bytes[0] = get_field(state.mip, MIP_MSIP);
 734         return true;
 735       }
 736       break;
 737   }
 738
 739   return false;
 740 }
 741
 742 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 743 {
 744   switch (addr)
 745   {
 746     case 0:
 747       if (len <= 4) {
 748         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 749         return true;
 750       }
 751       break;
 752   }
 753
 754   return false;
 755 }
 756
 757 void processor_t::trigger_updated()
 758 {
 759   mmu->flush_tlb();
 760   mmu->check_triggers_fetch = false;
 761   mmu->check_triggers_load = false;
 762   mmu->check_triggers_store = false;
 763
 764   for (unsigned i = 0; i < state.num_triggers; i++) {
 765     if (state.mcontrol[i].execute) {
 766       mmu->check_triggers_fetch = true;
 767     }
 768     if (state.mcontrol[i].load) {
 769       mmu->check_triggers_load = true;
 770     }
 771     if (state.mcontrol[i].store) {
 772       mmu->check_triggers_store = true;
 773     }
 774   }
 775 }