riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   fprintf(stderr, "Entering debug mode because of cause %d", cause);
 193   state.dcsr.cause = cause;
 194   state.dcsr.prv = state.prv;
 195   set_privilege(PRV_M);
 196   state.dpc = state.pc;
 197   state.pc = debug_rom_entry();
 198 }
 199
 200 void processor_t::take_trap(trap_t& t, reg_t epc)
 201 {
 202   if (debug) {
 203     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 204             id, t.name(), epc);
 205     if (t.has_badaddr())
 206       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 207           t.get_badaddr());
 208   }
 209
 210   if (state.dcsr.cause) {
 211     if (t.cause() == CAUSE_BREAKPOINT) {
 212       state.pc = debug_rom_entry();
 213       fprintf(stderr, "Breakpoint.");
 214     } else {
 215       fprintf(stderr, "WE ARE IN DEBUG MODE, DEBUG_ROM_EXCEPTION\n");
 216       state.pc = DEBUG_ROM_EXCEPTION;
 217     }
 218     return;
 219   }
 220
 221   if (t.cause() == CAUSE_BREAKPOINT && (
 222               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 223               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 224               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 225               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 226     enter_debug_mode(DCSR_CAUSE_SWBP);
 227     return;
 228   }
 229
 230   // by default, trap to M-mode, unless delegated to S-mode
 231   reg_t bit = t.cause();
 232   reg_t deleg = state.medeleg;
 233   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 234   if (interrupt)
 235     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 236   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 237     // handle the trap in S-mode
 238     state.pc = state.stvec;
 239     state.scause = t.cause();
 240     state.sepc = epc;
 241     if (t.has_badaddr())
 242       state.sbadaddr = t.get_badaddr();
 243
 244     reg_t s = state.mstatus;
 245     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 246     s = set_field(s, MSTATUS_SPP, state.prv);
 247     s = set_field(s, MSTATUS_SIE, 0);
 248     set_csr(CSR_MSTATUS, s);
 249     set_privilege(PRV_S);
 250   } else {
 251     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 252     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 253     state.mepc = epc;
 254     state.mcause = t.cause();
 255     if (t.has_badaddr())
 256       state.mbadaddr = t.get_badaddr();
 257
 258     reg_t s = state.mstatus;
 259     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 260     s = set_field(s, MSTATUS_MPP, state.prv);
 261     s = set_field(s, MSTATUS_MIE, 0);
 262     set_csr(CSR_MSTATUS, s);
 263     set_privilege(PRV_M);
 264   }
 265
 266   yield_load_reservation();
 267 }
 268
 269 void processor_t::disasm(insn_t insn)
 270 {
 271   static uint64_t last_pc = 1, last_bits;
 272   static uint64_t executions = 1;
 273
 274   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 275   if (last_pc != state.pc || last_bits != bits) {
 276     if (executions != 1) {
 277       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 278     }
 279
 280     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 281             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 282     last_pc = state.pc;
 283     last_bits = bits;
 284     executions = 1;
 285   } else {
 286     executions++;
 287   }
 288 }
 289
 290 int processor_t::paddr_bits()
 291 {
 292   assert(xlen == max_xlen);
 293   return max_xlen == 64 ? 50 : 34;
 294 }
 295
 296 void processor_t::set_csr(int which, reg_t val)
 297 {
 298   val = zext_xlen(val);
 299   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 300   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 301   switch (which)
 302   {
 303     case CSR_FFLAGS:
 304       dirty_fp_state;
 305       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 306       break;
 307     case CSR_FRM:
 308       dirty_fp_state;
 309       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 310       break;
 311     case CSR_FCSR:
 312       dirty_fp_state;
 313       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 314       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 315       break;
 316     case CSR_MSTATUS: {
 317       if ((val ^ state.mstatus) &
 318           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 319         mmu->flush_tlb();
 320
 321       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 322                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 323                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 324                  | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
 325
 326       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 327
 328       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 329       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 330       if (max_xlen == 32)
 331         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 332       else
 333         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 334
 335       // spike supports the notion of xlen < max_xlen, but current priv spec
 336       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 337       xlen = max_xlen;
 338       break;
 339     }
 340     case CSR_MIP: {
 341       reg_t mask = MIP_SSIP | MIP_STIP;
 342       state.mip = (state.mip & ~mask) | (val & mask);
 343       break;
 344     }
 345     case CSR_MIE:
 346       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 347       break;
 348     case CSR_MIDELEG:
 349       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 350       break;
 351     case CSR_MEDELEG: {
 352       reg_t mask = 0;
 353 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 354 #include "encoding.h"
 355 #undef DECLARE_CAUSE
 356       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 357       break;
 358     }
 359     case CSR_MINSTRET:
 360     case CSR_MCYCLE:
 361       if (xlen == 32)
 362         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 363       else
 364         state.minstret = val;
 365       break;
 366     case CSR_MINSTRETH:
 367     case CSR_MCYCLEH:
 368       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 369       break;
 370     case CSR_SCOUNTEREN:
 371       state.scounteren = val;
 372       break;
 373     case CSR_MCOUNTEREN:
 374       state.mcounteren = val;
 375       break;
 376     case CSR_SSTATUS: {
 377       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 378                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 379       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 380     }
 381     case CSR_SIP: {
 382       reg_t mask = MIP_SSIP & state.mideleg;
 383       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 384     }
 385     case CSR_SIE:
 386       return set_csr(CSR_MIE,
 387                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 388     case CSR_SPTBR: {
 389       mmu->flush_tlb();
 390       if (max_xlen == 32)
 391         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 392       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 393                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 394                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 395         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 396       break;
 397     }
 398     case CSR_SEPC: state.sepc = val; break;
 399     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 400     case CSR_SSCRATCH: state.sscratch = val; break;
 401     case CSR_SCAUSE: state.scause = val; break;
 402     case CSR_SBADADDR: state.sbadaddr = val; break;
 403     case CSR_MEPC: state.mepc = val; break;
 404     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 405     case CSR_MSCRATCH: state.mscratch = val; break;
 406     case CSR_MCAUSE: state.mcause = val; break;
 407     case CSR_MBADADDR: state.mbadaddr = val; break;
 408     case CSR_MISA: {
 409       if (!(val & (1L << ('F' - 'A'))))
 410         val &= ~(1L << ('D' - 'A'));
 411
 412       // allow MAFDC bits in MISA to be modified
 413       reg_t mask = 0;
 414       mask |= 1L << ('M' - 'A');
 415       mask |= 1L << ('A' - 'A');
 416       mask |= 1L << ('F' - 'A');
 417       mask |= 1L << ('D' - 'A');
 418       mask |= 1L << ('C' - 'A');
 419       mask &= max_isa;
 420
 421       isa = (val & mask) | (isa & ~mask);
 422       break;
 423     }
 424     case CSR_TSELECT:
 425       if (val < state.num_triggers) {
 426         state.tselect = val;
 427       }
 428       break;
 429     case CSR_TDATA1:
 430       {
 431         mcontrol_t *mc = &state.mcontrol[state.tselect];
 432         if (mc->dmode && !state.dcsr.cause) {
 433           break;
 434         }
 435         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 436         mc->select = get_field(val, MCONTROL_SELECT);
 437         mc->timing = get_field(val, MCONTROL_TIMING);
 438         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 439         mc->chain = get_field(val, MCONTROL_CHAIN);
 440         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 441         mc->m = get_field(val, MCONTROL_M);
 442         mc->h = get_field(val, MCONTROL_H);
 443         mc->s = get_field(val, MCONTROL_S);
 444         mc->u = get_field(val, MCONTROL_U);
 445         mc->execute = get_field(val, MCONTROL_EXECUTE);
 446         mc->store = get_field(val, MCONTROL_STORE);
 447         mc->load = get_field(val, MCONTROL_LOAD);
 448         // Assume we're here because of csrw.
 449         if (mc->execute)
 450           mc->timing = 0;
 451         trigger_updated();
 452       }
 453       break;
 454     case CSR_TDATA2:
 455       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 456         break;
 457       }
 458       if (state.tselect < state.num_triggers) {
 459         state.tdata2[state.tselect] = val;
 460       }
 461       break;
 462     case CSR_DCSR:
 463       state.dcsr.prv = get_field(val, DCSR_PRV);
 464       state.dcsr.step = get_field(val, DCSR_STEP);
 465       // TODO: ndreset and fullreset
 466       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 467       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 468       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 469       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 470       state.dcsr.halt = get_field(val, DCSR_HALT);
 471       break;
 472     case CSR_DPC:
 473       state.dpc = val;
 474       break;
 475     case CSR_DSCRATCH:
 476       state.dscratch = val;
 477       break;
 478   }
 479 }
 480
 481 reg_t processor_t::get_csr(int which)
 482 {
 483   uint32_t ctr_en = -1;
 484   if (state.prv < PRV_M)
 485     ctr_en &= state.mcounteren;
 486   if (state.prv < PRV_S)
 487     ctr_en &= state.scounteren;
 488   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 489
 490   if (ctr_ok) {
 491     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 492       return 0;
 493     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 494       return 0;
 495   }
 496   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 497     return 0;
 498   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 499     return 0;
 500   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 501     return 0;
 502
 503   switch (which)
 504   {
 505     case CSR_FFLAGS:
 506       require_fp;
 507       if (!supports_extension('F'))
 508         break;
 509       return state.fflags;
 510     case CSR_FRM:
 511       require_fp;
 512       if (!supports_extension('F'))
 513         break;
 514       return state.frm;
 515     case CSR_FCSR:
 516       require_fp;
 517       if (!supports_extension('F'))
 518         break;
 519       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 520     case CSR_INSTRET:
 521     case CSR_CYCLE:
 522       if (ctr_ok)
 523         return state.minstret;
 524       break;
 525     case CSR_MINSTRET:
 526     case CSR_MCYCLE:
 527       return state.minstret;
 528     case CSR_MINSTRETH:
 529     case CSR_MCYCLEH:
 530       if (xlen == 32)
 531         return state.minstret >> 32;
 532       break;
 533     case CSR_SCOUNTEREN: return state.scounteren;
 534     case CSR_MCOUNTEREN: return state.mcounteren;
 535     case CSR_SSTATUS: {
 536       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 537                  | SSTATUS_XS | SSTATUS_SUM;
 538       reg_t sstatus = state.mstatus & mask;
 539       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 540           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 541         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 542       return sstatus;
 543     }
 544     case CSR_SIP: return state.mip & state.mideleg;
 545     case CSR_SIE: return state.mie & state.mideleg;
 546     case CSR_SEPC: return state.sepc;
 547     case CSR_SBADADDR: return state.sbadaddr;
 548     case CSR_STVEC: return state.stvec;
 549     case CSR_SCAUSE:
 550       if (max_xlen > xlen)
 551         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 552       return state.scause;
 553     case CSR_SPTBR:
 554       if (get_field(state.mstatus, MSTATUS_TVM))
 555         require_privilege(PRV_M);
 556       return state.sptbr;
 557     case CSR_SSCRATCH: return state.sscratch;
 558     case CSR_MSTATUS: return state.mstatus;
 559     case CSR_MIP: return state.mip;
 560     case CSR_MIE: return state.mie;
 561     case CSR_MEPC: return state.mepc;
 562     case CSR_MSCRATCH: return state.mscratch;
 563     case CSR_MCAUSE: return state.mcause;
 564     case CSR_MBADADDR: return state.mbadaddr;
 565     case CSR_MISA: return isa;
 566     case CSR_MARCHID: return 0;
 567     case CSR_MIMPID: return 0;
 568     case CSR_MVENDORID: return 0;
 569     case CSR_MHARTID: return id;
 570     case CSR_MTVEC: return state.mtvec;
 571     case CSR_MEDELEG: return state.medeleg;
 572     case CSR_MIDELEG: return state.mideleg;
 573     case CSR_TSELECT: return state.tselect;
 574     case CSR_TDATA1:
 575       if (state.tselect < state.num_triggers) {
 576         reg_t v = 0;
 577         mcontrol_t *mc = &state.mcontrol[state.tselect];
 578         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 579         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 580         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 581         v = set_field(v, MCONTROL_SELECT, mc->select);
 582         v = set_field(v, MCONTROL_TIMING, mc->timing);
 583         v = set_field(v, MCONTROL_ACTION, mc->action);
 584         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 585         v = set_field(v, MCONTROL_MATCH, mc->match);
 586         v = set_field(v, MCONTROL_M, mc->m);
 587         v = set_field(v, MCONTROL_H, mc->h);
 588         v = set_field(v, MCONTROL_S, mc->s);
 589         v = set_field(v, MCONTROL_U, mc->u);
 590         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 591         v = set_field(v, MCONTROL_STORE, mc->store);
 592         v = set_field(v, MCONTROL_LOAD, mc->load);
 593         return v;
 594       } else {
 595         return 0;
 596       }
 597       break;
 598     case CSR_TDATA2:
 599       if (state.tselect < state.num_triggers) {
 600         return state.tdata2[state.tselect];
 601       } else {
 602         return 0;
 603       }
 604       break;
 605     case CSR_TDATA3: return 0;
 606     case CSR_DCSR:
 607       {
 608         uint32_t v = 0;
 609         v = set_field(v, DCSR_XDEBUGVER, 1);
 610         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 611         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 612         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 613         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 614         v = set_field(v, DCSR_STOPCYCLE, 0);
 615         v = set_field(v, DCSR_STOPTIME, 0);
 616         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 617         v = set_field(v, DCSR_STEP, state.dcsr.step);
 618         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 619         return v;
 620       }
 621     case CSR_DPC:
 622       return state.dpc;
 623     case CSR_DSCRATCH:
 624       return state.dscratch;
 625   }
 626   throw trap_illegal_instruction(0);
 627 }
 628
 629 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 630 {
 631   throw trap_illegal_instruction(0);
 632 }
 633
 634 insn_func_t processor_t::decode_insn(insn_t insn)
 635 {
 636   // look up opcode in hash table
 637   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 638   insn_desc_t desc = opcode_cache[idx];
 639
 640   if (unlikely(insn.bits() != desc.match)) {
 641     // fall back to linear search
 642     insn_desc_t* p = &instructions[0];
 643     while ((insn.bits() & p->mask) != p->match)
 644       p++;
 645     desc = *p;
 646
 647     if (p->mask != 0 && p > &instructions[0]) {
 648       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 649         // move to front of opcode list to reduce miss penalty
 650         while (--p >= &instructions[0])
 651           *(p+1) = *p;
 652         instructions[0] = desc;
 653       }
 654     }
 655
 656     opcode_cache[idx] = desc;
 657     opcode_cache[idx].match = insn.bits();
 658   }
 659
 660   return xlen == 64 ? desc.rv64 : desc.rv32;
 661 }
 662
 663 void processor_t::register_insn(insn_desc_t desc)
 664 {
 665   instructions.push_back(desc);
 666 }
 667
 668 void processor_t::build_opcode_map()
 669 {
 670   struct cmp {
 671     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 672       if (lhs.match == rhs.match)
 673         return lhs.mask > rhs.mask;
 674       return lhs.match > rhs.match;
 675     }
 676   };
 677   std::sort(instructions.begin(), instructions.end(), cmp());
 678
 679   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 680     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 681 }
 682
 683 void processor_t::register_extension(extension_t* x)
 684 {
 685   for (auto insn : x->get_instructions())
 686     register_insn(insn);
 687   build_opcode_map();
 688   for (auto disasm_insn : x->get_disasms())
 689     disassembler->add_insn(disasm_insn);
 690   if (ext != NULL)
 691     throw std::logic_error("only one extension may be registered");
 692   ext = x;
 693   x->set_processor(this);
 694 }
 695
 696 void processor_t::register_base_instructions()
 697 {
 698   #define DECLARE_INSN(name, match, mask) \
 699     insn_bits_t name##_match = (match), name##_mask = (mask);
 700   #include "encoding.h"
 701   #undef DECLARE_INSN
 702
 703   #define DEFINE_INSN(name) \
 704     REGISTER_INSN(this, name, name##_match, name##_mask)
 705   #include "insn_list.h"
 706   #undef DEFINE_INSN
 707
 708   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 709   build_opcode_map();
 710 }
 711
 712 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 713 {
 714   switch (addr)
 715   {
 716     case 0:
 717       if (len <= 4) {
 718         memset(bytes, 0, len);
 719         bytes[0] = get_field(state.mip, MIP_MSIP);
 720         return true;
 721       }
 722       break;
 723   }
 724
 725   return false;
 726 }
 727
 728 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 729 {
 730   switch (addr)
 731   {
 732     case 0:
 733       if (len <= 4) {
 734         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 735         return true;
 736       }
 737       break;
 738   }
 739
 740   return false;
 741 }
 742
 743 void processor_t::trigger_updated()
 744 {
 745   mmu->flush_tlb();
 746   mmu->check_triggers_fetch = false;
 747   mmu->check_triggers_load = false;
 748   mmu->check_triggers_store = false;
 749
 750   for (unsigned i = 0; i < state.num_triggers; i++) {
 751     if (state.mcontrol[i].execute) {
 752       mmu->check_triggers_fetch = true;
 753     }
 754     if (state.mcontrol[i].load) {
 755       mmu->check_triggers_load = true;
 756     }
 757     if (state.mcontrol[i].store) {
 758       mmu->check_triggers_store = true;
 759     }
 760   }
 761 }