riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   mtvec = DEFAULT_MTVEC;
 119   load_reservation = -1;
 120 }
 121
 122 void processor_t::set_debug(bool value)
 123 {
 124   debug = value;
 125   if (ext)
 126     ext->set_debug(value);
 127 }
 128
 129 void processor_t::set_histogram(bool value)
 130 {
 131   histogram_enabled = value;
 132 #ifndef RISCV_ENABLE_HISTOGRAM
 133   if (value) {
 134     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 135     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 136   }
 137 #endif
 138 }
 139
 140 void processor_t::reset()
 141 {
 142   state.reset();
 143   state.dcsr.halt = halt_on_reset;
 144   halt_on_reset = false;
 145   set_csr(CSR_MSTATUS, state.mstatus);
 146
 147   if (ext)
 148     ext->reset(); // reset the extension
 149 }
 150
 151 void processor_t::raise_interrupt(reg_t which)
 152 {
 153   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 154 }
 155
 156 static int ctz(reg_t val)
 157 {
 158   int res = 0;
 159   if (val)
 160     while ((val & 1) == 0)
 161       val >>= 1, res++;
 162   return res;
 163 }
 164
 165 void processor_t::take_interrupt()
 166 {
 167   reg_t pending_interrupts = state.mip & state.mie;
 168
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 171   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 172
 173   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 174   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 175   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     raise_interrupt(ctz(enabled_interrupts));
 179 }
 180
 181 static bool validate_priv(reg_t priv)
 182 {
 183   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 184 }
 185
 186 void processor_t::set_privilege(reg_t prv)
 187 {
 188   assert(validate_priv(prv));
 189   mmu->flush_tlb();
 190   state.prv = prv;
 191 }
 192
 193 void processor_t::enter_debug_mode(uint8_t cause)
 194 {
 195   state.dcsr.cause = cause;
 196   state.dcsr.prv = state.prv;
 197   set_privilege(PRV_M);
 198   state.dpc = state.pc;
 199   state.pc = DEBUG_ROM_START;
 200   //debug = true; // TODO
 201 }
 202
 203 void processor_t::take_trap(trap_t& t, reg_t epc)
 204 {
 205   if (debug) {
 206     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 207             id, t.name(), epc);
 208     if (t.has_badaddr())
 209       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 210           t.get_badaddr());
 211   }
 212
 213   if (t.cause() == CAUSE_BREAKPOINT && (
 214               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 215               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 216               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 217               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 218     enter_debug_mode(DCSR_CAUSE_SWBP);
 219     return;
 220   }
 221
 222   if (state.dcsr.cause) {
 223     state.pc = DEBUG_ROM_EXCEPTION;
 224     return;
 225   }
 226
 227   // by default, trap to M-mode, unless delegated to S-mode
 228   reg_t bit = t.cause();
 229   reg_t deleg = state.medeleg;
 230   if (bit & ((reg_t)1 << (max_xlen-1)))
 231     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 232   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 233     // handle the trap in S-mode
 234     state.pc = state.stvec;
 235     state.scause = t.cause();
 236     state.sepc = epc;
 237     if (t.has_badaddr())
 238       state.sbadaddr = t.get_badaddr();
 239
 240     reg_t s = state.mstatus;
 241     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 242     s = set_field(s, MSTATUS_SPP, state.prv);
 243     s = set_field(s, MSTATUS_SIE, 0);
 244     set_csr(CSR_MSTATUS, s);
 245     set_privilege(PRV_S);
 246   } else {
 247     state.pc = state.mtvec;
 248     state.mepc = epc;
 249     state.mcause = t.cause();
 250     if (t.has_badaddr())
 251       state.mbadaddr = t.get_badaddr();
 252
 253     reg_t s = state.mstatus;
 254     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 255     s = set_field(s, MSTATUS_MPP, state.prv);
 256     s = set_field(s, MSTATUS_MIE, 0);
 257     set_csr(CSR_MSTATUS, s);
 258     set_privilege(PRV_M);
 259   }
 260
 261   yield_load_reservation();
 262 }
 263
 264 void processor_t::disasm(insn_t insn)
 265 {
 266   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 267   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 268           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 269 }
 270
 271 static bool validate_vm(int max_xlen, reg_t vm)
 272 {
 273   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 274     return true;
 275   if (max_xlen == 32 && vm == VM_SV32)
 276     return true;
 277   return vm == VM_MBARE;
 278 }
 279
 280 int processor_t::paddr_bits()
 281 {
 282   assert(xlen == max_xlen);
 283   return max_xlen == 64 ? 50 : 34;
 284 }
 285
 286 void processor_t::set_csr(int which, reg_t val)
 287 {
 288   val = zext_xlen(val);
 289   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 290   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 291   switch (which)
 292   {
 293     case CSR_FFLAGS:
 294       dirty_fp_state;
 295       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 296       break;
 297     case CSR_FRM:
 298       dirty_fp_state;
 299       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 300       break;
 301     case CSR_FCSR:
 302       dirty_fp_state;
 303       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 304       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 305       break;
 306     case CSR_MSTATUS: {
 307       if ((val ^ state.mstatus) &
 308           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 309         mmu->flush_tlb();
 310
 311       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 312                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 313                  | (ext ? MSTATUS_XS : 0);
 314
 315       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 316         mask |= MSTATUS_VM;
 317       if (validate_priv(get_field(val, MSTATUS_MPP)))
 318         mask |= MSTATUS_MPP;
 319
 320       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 321
 322       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 323       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 324       if (max_xlen == 32)
 325         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 326       else
 327         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 328
 329       // spike supports the notion of xlen < max_xlen, but current priv spec
 330       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 331       xlen = max_xlen;
 332       break;
 333     }
 334     case CSR_MIP: {
 335       reg_t mask = MIP_SSIP | MIP_STIP;
 336       state.mip = (state.mip & ~mask) | (val & mask);
 337       break;
 338     }
 339     case CSR_MIE:
 340       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 341       break;
 342     case CSR_MIDELEG:
 343       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 344       break;
 345     case CSR_MEDELEG: {
 346       reg_t mask = 0;
 347 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 348 #include "encoding.h"
 349 #undef DECLARE_CAUSE
 350       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 351       break;
 352     }
 353     case CSR_MUCOUNTEREN:
 354       state.mucounteren = val & 7;
 355       break;
 356     case CSR_MSCOUNTEREN:
 357       state.mscounteren = val & 7;
 358       break;
 359     case CSR_SSTATUS: {
 360       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 361                  | SSTATUS_XS | SSTATUS_PUM;
 362       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 363     }
 364     case CSR_SIP:
 365       return set_csr(CSR_MIP,
 366                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 367     case CSR_SIE:
 368       return set_csr(CSR_MIE,
 369                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 370     case CSR_SPTBR: {
 371       // upper bits of sptbr are the ASID; we only support ASID = 0
 372       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 373       break;
 374     }
 375     case CSR_SEPC: state.sepc = val; break;
 376     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 377     case CSR_SSCRATCH: state.sscratch = val; break;
 378     case CSR_SCAUSE: state.scause = val; break;
 379     case CSR_SBADADDR: state.sbadaddr = val; break;
 380     case CSR_MEPC: state.mepc = val; break;
 381     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 382     case CSR_MSCRATCH: state.mscratch = val; break;
 383     case CSR_MCAUSE: state.mcause = val; break;
 384     case CSR_MBADADDR: state.mbadaddr = val; break;
 385     case CSR_DCSR:
 386       state.dcsr.prv = get_field(val, DCSR_PRV);
 387       state.dcsr.step = get_field(val, DCSR_STEP);
 388       // TODO: ndreset and fullreset
 389       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 390       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 391       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 392       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 393       state.dcsr.halt = get_field(val, DCSR_HALT);
 394       break;
 395     case CSR_DPC:
 396       state.dpc = val;
 397       break;
 398     case CSR_DSCRATCH:
 399       state.dscratch = val;
 400       break;
 401   }
 402 }
 403
 404 reg_t processor_t::get_csr(int which)
 405 {
 406   switch (which)
 407   {
 408     case CSR_FFLAGS:
 409       require_fp;
 410       if (!supports_extension('F'))
 411         break;
 412       return state.fflags;
 413     case CSR_FRM:
 414       require_fp;
 415       if (!supports_extension('F'))
 416         break;
 417       return state.frm;
 418     case CSR_FCSR:
 419       require_fp;
 420       if (!supports_extension('F'))
 421         break;
 422       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 423     case CSR_TIME:
 424     case CSR_INSTRET:
 425     case CSR_CYCLE:
 426       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 427         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 428       break;
 429     case CSR_STIME:
 430     case CSR_SINSTRET:
 431     case CSR_SCYCLE:
 432       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 433         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 434       break;
 435     case CSR_MUCOUNTEREN: return state.mucounteren;
 436     case CSR_MSCOUNTEREN: return state.mscounteren;
 437     case CSR_MUCYCLE_DELTA: return 0;
 438     case CSR_MUTIME_DELTA: return 0;
 439     case CSR_MUINSTRET_DELTA: return 0;
 440     case CSR_MSCYCLE_DELTA: return 0;
 441     case CSR_MSTIME_DELTA: return 0;
 442     case CSR_MSINSTRET_DELTA: return 0;
 443     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 444     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 445     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 446     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 447     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 448     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 449     case CSR_MCYCLE: return state.minstret;
 450     case CSR_MINSTRET: return state.minstret;
 451     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 452     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 453     case CSR_SSTATUS: {
 454       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 455                  | SSTATUS_XS | SSTATUS_PUM;
 456       reg_t sstatus = state.mstatus & mask;
 457       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 458           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 459         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 460       return sstatus;
 461     }
 462     case CSR_SIP: return state.mip & state.mideleg;
 463     case CSR_SIE: return state.mie & state.mideleg;
 464     case CSR_SEPC: return state.sepc;
 465     case CSR_SBADADDR: return state.sbadaddr;
 466     case CSR_STVEC: return state.stvec;
 467     case CSR_SCAUSE:
 468       if (max_xlen > xlen)
 469         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 470       return state.scause;
 471     case CSR_SPTBR: return state.sptbr;
 472     case CSR_SSCRATCH: return state.sscratch;
 473     case CSR_MSTATUS: return state.mstatus;
 474     case CSR_MIP: return state.mip;
 475     case CSR_MIE: return state.mie;
 476     case CSR_MEPC: return state.mepc;
 477     case CSR_MSCRATCH: return state.mscratch;
 478     case CSR_MCAUSE: return state.mcause;
 479     case CSR_MBADADDR: return state.mbadaddr;
 480     case CSR_MISA: return isa;
 481     case CSR_MARCHID: return 0;
 482     case CSR_MIMPID: return 0;
 483     case CSR_MVENDORID: return 0;
 484     case CSR_MHARTID: return id;
 485     case CSR_MTVEC: return state.mtvec;
 486     case CSR_MEDELEG: return state.medeleg;
 487     case CSR_MIDELEG: return state.mideleg;
 488     case CSR_TDRSELECT: return 0;
 489     case CSR_DCSR:
 490       {
 491         uint32_t v = 0;
 492         v = set_field(v, DCSR_XDEBUGVER, 1);
 493         v = set_field(v, DCSR_HWBPCOUNT, 0);
 494         v = set_field(v, DCSR_NDRESET, 0);
 495         v = set_field(v, DCSR_FULLRESET, 0);
 496         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 497         v = set_field(v, DCSR_STEP, state.dcsr.step);
 498         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 499         v = set_field(v, DCSR_STOPCYCLE, 0);
 500         v = set_field(v, DCSR_STOPTIME, 0);
 501         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 502         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 503         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 504         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 505         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 506         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 507         return v;
 508       }
 509     case CSR_DPC:
 510       return state.dpc;
 511     case CSR_DSCRATCH:
 512       return state.dscratch;
 513   }
 514   throw trap_illegal_instruction();
 515 }
 516
 517 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 518 {
 519   throw trap_illegal_instruction();
 520 }
 521
 522 insn_func_t processor_t::decode_insn(insn_t insn)
 523 {
 524   // look up opcode in hash table
 525   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 526   insn_desc_t desc = opcode_cache[idx];
 527
 528   if (unlikely(insn.bits() != desc.match)) {
 529     // fall back to linear search
 530     insn_desc_t* p = &instructions[0];
 531     while ((insn.bits() & p->mask) != p->match)
 532       p++;
 533     desc = *p;
 534
 535     if (p->mask != 0 && p > &instructions[0]) {
 536       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 537         // move to front of opcode list to reduce miss penalty
 538         while (--p >= &instructions[0])
 539           *(p+1) = *p;
 540         instructions[0] = desc;
 541       }
 542     }
 543
 544     opcode_cache[idx] = desc;
 545     opcode_cache[idx].match = insn.bits();
 546   }
 547
 548   return xlen == 64 ? desc.rv64 : desc.rv32;
 549 }
 550
 551 void processor_t::register_insn(insn_desc_t desc)
 552 {
 553   instructions.push_back(desc);
 554 }
 555
 556 void processor_t::build_opcode_map()
 557 {
 558   struct cmp {
 559     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 560       if (lhs.match == rhs.match)
 561         return lhs.mask > rhs.mask;
 562       return lhs.match > rhs.match;
 563     }
 564   };
 565   std::sort(instructions.begin(), instructions.end(), cmp());
 566
 567   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 568     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 569 }
 570
 571 void processor_t::register_extension(extension_t* x)
 572 {
 573   for (auto insn : x->get_instructions())
 574     register_insn(insn);
 575   build_opcode_map();
 576   for (auto disasm_insn : x->get_disasms())
 577     disassembler->add_insn(disasm_insn);
 578   if (ext != NULL)
 579     throw std::logic_error("only one extension may be registered");
 580   ext = x;
 581   x->set_processor(this);
 582 }
 583
 584 void processor_t::register_base_instructions()
 585 {
 586   #define DECLARE_INSN(name, match, mask) \
 587     insn_bits_t name##_match = (match), name##_mask = (mask);
 588   #include "encoding.h"
 589   #undef DECLARE_INSN
 590
 591   #define DEFINE_INSN(name) \
 592     REGISTER_INSN(this, name, name##_match, name##_mask)
 593   #include "insn_list.h"
 594   #undef DEFINE_INSN
 595
 596   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 597   build_opcode_map();
 598 }
 599
 600 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 601 {
 602   return false;
 603 }
 604
 605 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 606 {
 607   switch (addr)
 608   {
 609     case 0:
 610       state.mip &= ~MIP_MSIP;
 611       if (bytes[0] & 1)
 612         state.mip |= MIP_MSIP;
 613       return true;
 614
 615     default:
 616       return false;
 617   }
 618 }