riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  24   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  25     id(id), run(false), debug(false)
  26 {
  27   parse_isa_string(isa);
  28
  29   mmu = new mmu_t(sim, this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   load_reservation = -1;
 119 }
 120
 121 void processor_t::set_debug(bool value)
 122 {
 123   debug = value;
 124   if (ext)
 125     ext->set_debug(value);
 126 }
 127
 128 void processor_t::set_histogram(bool value)
 129 {
 130   histogram_enabled = value;
 131 #ifndef RISCV_ENABLE_HISTOGRAM
 132   if (value) {
 133     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 134     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 135   }
 136 #endif
 137 }
 138
 139 void processor_t::reset(bool value)
 140 {
 141   if (run == !value)
 142     return;
 143   run = !value;
 144
 145   state.reset();
 146   set_csr(CSR_MSTATUS, state.mstatus);
 147
 148   if (ext)
 149     ext->reset(); // reset the extension
 150 }
 151
 152 void processor_t::raise_interrupt(reg_t which)
 153 {
 154   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 155 }
 156
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt()
 167 {
 168   reg_t pending_interrupts = state.mip & state.mie;
 169
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 177
 178   if (enabled_interrupts)
 179     raise_interrupt(ctz(enabled_interrupts));
 180 }
 181
 182 static bool validate_priv(reg_t priv)
 183 {
 184   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 185 }
 186
 187 void processor_t::set_privilege(reg_t prv)
 188 {
 189   assert(validate_priv(prv));
 190   mmu->flush_tlb();
 191   state.prv = prv;
 192 }
 193
 194 void processor_t::take_trap(trap_t& t, reg_t epc)
 195 {
 196   if (debug)
 197     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 198             id, t.name(), epc);
 199
 200   // by default, trap to M-mode, unless delegated to S-mode
 201   reg_t bit = t.cause();
 202   reg_t deleg = state.medeleg;
 203   if (bit & ((reg_t)1 << (max_xlen-1)))
 204     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 205   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 206     // handle the trap in S-mode
 207     state.pc = state.stvec;
 208     state.scause = t.cause();
 209     state.sepc = epc;
 210     if (t.has_badaddr())
 211       state.sbadaddr = t.get_badaddr();
 212
 213     reg_t s = state.mstatus;
 214     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 215     s = set_field(s, MSTATUS_SPP, state.prv);
 216     s = set_field(s, MSTATUS_SIE, 0);
 217     set_csr(CSR_MSTATUS, s);
 218     set_privilege(PRV_S);
 219   } else {
 220     state.pc = state.mtvec;
 221     state.mcause = t.cause();
 222     state.mepc = epc;
 223     if (t.has_badaddr())
 224       state.mbadaddr = t.get_badaddr();
 225
 226     reg_t s = state.mstatus;
 227     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 228     s = set_field(s, MSTATUS_MPP, state.prv);
 229     s = set_field(s, MSTATUS_MIE, 0);
 230     set_csr(CSR_MSTATUS, s);
 231     set_privilege(PRV_M);
 232   }
 233
 234   yield_load_reservation();
 235 }
 236
 237 void processor_t::disasm(insn_t insn)
 238 {
 239   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 240   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 241           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 242 }
 243
 244 static bool validate_vm(int max_xlen, reg_t vm)
 245 {
 246   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 247     return true;
 248   if (max_xlen == 32 && vm == VM_SV32)
 249     return true;
 250   return vm == VM_MBARE;
 251 }
 252
 253 void processor_t::set_csr(int which, reg_t val)
 254 {
 255   val = zext_xlen(val);
 256   reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
 257   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 258   switch (which)
 259   {
 260     case CSR_FFLAGS:
 261       dirty_fp_state;
 262       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 263       break;
 264     case CSR_FRM:
 265       dirty_fp_state;
 266       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 267       break;
 268     case CSR_FCSR:
 269       dirty_fp_state;
 270       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 271       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 272       break;
 273     case CSR_MSTATUS: {
 274       if ((val ^ state.mstatus) &
 275           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 276         mmu->flush_tlb();
 277
 278       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 279                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 280                  | (ext ? MSTATUS_XS : 0);
 281
 282       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 283         mask |= MSTATUS_VM;
 284       if (validate_priv(get_field(val, MSTATUS_MPP)))
 285         mask |= MSTATUS_MPP;
 286
 287       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 288
 289       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 290       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 291       if (max_xlen == 32)
 292         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 293       else
 294         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 295
 296       // spike supports the notion of xlen < max_xlen, but current priv spec
 297       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 298       xlen = max_xlen;
 299       break;
 300     }
 301     case CSR_MIP: {
 302       reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
 303       state.mip = (state.mip & ~mask) | (val & mask);
 304       break;
 305     }
 306     case CSR_MIPI:
 307       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 308       break;
 309     case CSR_MIE:
 310       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 311       break;
 312     case CSR_MIDELEG:
 313       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 314       break;
 315     case CSR_MEDELEG: {
 316       reg_t mask = 0;
 317 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 318 #include "encoding.h"
 319 #undef DECLARE_CAUSE
 320       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 321       break;
 322     }
 323     case CSR_MUCOUNTEREN:
 324       state.mucounteren = val & 7;
 325       break;
 326     case CSR_MSCOUNTEREN:
 327       state.mscounteren = val & 7;
 328       break;
 329     case CSR_SSTATUS: {
 330       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 331                  | SSTATUS_XS | SSTATUS_PUM;
 332       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 333     }
 334     case CSR_SIP:
 335       return set_csr(CSR_MIP,
 336                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 337     case CSR_SIE:
 338       return set_csr(CSR_MIE,
 339                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 340     case CSR_SEPC: state.sepc = val; break;
 341     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 342     case CSR_SPTBR: state.sptbr = val; break;
 343     case CSR_SSCRATCH: state.sscratch = val; break;
 344     case CSR_SCAUSE: state.scause = val; break;
 345     case CSR_SBADADDR: state.sbadaddr = val; break;
 346     case CSR_MEPC: state.mepc = val; break;
 347     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 348     case CSR_MSCRATCH: state.mscratch = val; break;
 349     case CSR_MCAUSE: state.mcause = val; break;
 350     case CSR_MBADADDR: state.mbadaddr = val; break;
 351     case CSR_MTOHOST:
 352       if (state.tohost == 0)
 353         state.tohost = val;
 354       break;
 355     case CSR_MFROMHOST:
 356       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 357       state.fromhost = val;
 358       break;
 359   }
 360 }
 361
 362 reg_t processor_t::get_csr(int which)
 363 {
 364   switch (which)
 365   {
 366     case CSR_FFLAGS:
 367       require_fp;
 368       if (!supports_extension('F'))
 369         break;
 370       return state.fflags;
 371     case CSR_FRM:
 372       require_fp;
 373       if (!supports_extension('F'))
 374         break;
 375       return state.frm;
 376     case CSR_FCSR:
 377       require_fp;
 378       if (!supports_extension('F'))
 379         break;
 380       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 381     case CSR_TIME:
 382     case CSR_INSTRET:
 383     case CSR_CYCLE:
 384       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 385         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 386       break;
 387     case CSR_STIME:
 388     case CSR_SINSTRET:
 389     case CSR_SCYCLE:
 390       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 391         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 392       break;
 393     case CSR_MUCOUNTEREN: return state.mucounteren;
 394     case CSR_MSCOUNTEREN: return state.mscounteren;
 395     case CSR_MUCYCLE_DELTA: return 0;
 396     case CSR_MUTIME_DELTA: return 0;
 397     case CSR_MUINSTRET_DELTA: return 0;
 398     case CSR_MSCYCLE_DELTA: return 0;
 399     case CSR_MSTIME_DELTA: return 0;
 400     case CSR_MSINSTRET_DELTA: return 0;
 401     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 402     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 403     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 404     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 405     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 406     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 407     case CSR_MCYCLE: return state.minstret;
 408     case CSR_MINSTRET: return state.minstret;
 409     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 410     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 411     case CSR_SSTATUS: {
 412       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 413                  | SSTATUS_XS | SSTATUS_PUM;
 414       reg_t sstatus = state.mstatus & mask;
 415       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 416           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 417         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 418       return sstatus;
 419     }
 420     case CSR_SIP: return state.mip & state.mideleg;
 421     case CSR_SIE: return state.mie & state.mideleg;
 422     case CSR_SEPC: return state.sepc;
 423     case CSR_SBADADDR: return state.sbadaddr;
 424     case CSR_STVEC: return state.stvec;
 425     case CSR_SCAUSE:
 426       if (max_xlen > xlen)
 427         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 428       return state.scause;
 429     case CSR_SPTBR: return state.sptbr;
 430     case CSR_SASID: return 0;
 431     case CSR_SSCRATCH: return state.sscratch;
 432     case CSR_MSTATUS: return state.mstatus;
 433     case CSR_MIP: return state.mip;
 434     case CSR_MIPI: return 0;
 435     case CSR_MIE: return state.mie;
 436     case CSR_MEPC: return state.mepc;
 437     case CSR_MSCRATCH: return state.mscratch;
 438     case CSR_MCAUSE: return state.mcause;
 439     case CSR_MBADADDR: return state.mbadaddr;
 440     case CSR_MISA: return isa;
 441     case CSR_MARCHID: return 0;
 442     case CSR_MIMPID: return 0;
 443     case CSR_MVENDORID: return 0;
 444     case CSR_MHARTID: return id;
 445     case CSR_MTVEC: return state.mtvec;
 446     case CSR_MEDELEG: return state.medeleg;
 447     case CSR_MIDELEG: return state.mideleg;
 448     case CSR_MTOHOST:
 449       sim->get_htif()->tick(); // not necessary, but faster
 450       return state.tohost;
 451     case CSR_MFROMHOST:
 452       sim->get_htif()->tick(); // not necessary, but faster
 453       return state.fromhost;
 454   }
 455   throw trap_illegal_instruction();
 456 }
 457
 458 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 459 {
 460   throw trap_illegal_instruction();
 461 }
 462
 463 insn_func_t processor_t::decode_insn(insn_t insn)
 464 {
 465   // look up opcode in hash table
 466   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 467   insn_desc_t desc = opcode_cache[idx];
 468
 469   if (unlikely(insn.bits() != desc.match)) {
 470     // fall back to linear search
 471     insn_desc_t* p = &instructions[0];
 472     while ((insn.bits() & p->mask) != p->match)
 473       p++;
 474     desc = *p;
 475
 476     if (p->mask != 0 && p > &instructions[0]) {
 477       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 478         // move to front of opcode list to reduce miss penalty
 479         while (--p >= &instructions[0])
 480           *(p+1) = *p;
 481         instructions[0] = desc;
 482       }
 483     }
 484
 485     opcode_cache[idx] = desc;
 486     opcode_cache[idx].match = insn.bits();
 487   }
 488
 489   return xlen == 64 ? desc.rv64 : desc.rv32;
 490 }
 491
 492 void processor_t::register_insn(insn_desc_t desc)
 493 {
 494   instructions.push_back(desc);
 495 }
 496
 497 void processor_t::build_opcode_map()
 498 {
 499   struct cmp {
 500     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 501       if (lhs.match == rhs.match)
 502         return lhs.mask > rhs.mask;
 503       return lhs.match > rhs.match;
 504     }
 505   };
 506   std::sort(instructions.begin(), instructions.end(), cmp());
 507
 508   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 509     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 510 }
 511
 512 void processor_t::register_extension(extension_t* x)
 513 {
 514   for (auto insn : x->get_instructions())
 515     register_insn(insn);
 516   build_opcode_map();
 517   for (auto disasm_insn : x->get_disasms())
 518     disassembler->add_insn(disasm_insn);
 519   if (ext != NULL)
 520     throw std::logic_error("only one extension may be registered");
 521   ext = x;
 522   x->set_processor(this);
 523 }
 524
 525 void processor_t::register_base_instructions()
 526 {
 527   #define DECLARE_INSN(name, match, mask) \
 528     insn_bits_t name##_match = (match), name##_mask = (mask);
 529   #include "encoding.h"
 530   #undef DECLARE_INSN
 531
 532   #define DEFINE_INSN(name) \
 533     REGISTER_INSN(this, name, name##_match, name##_mask)
 534   #include "insn_list.h"
 535   #undef DEFINE_INSN
 536
 537   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 538   build_opcode_map();
 539 }
 540
 541 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 542 {
 543   try {
 544     auto res = get_csr(addr / (max_xlen / 8));
 545     memcpy(bytes, &res, len);
 546     return true;
 547   } catch (trap_illegal_instruction& t) {
 548     return false;
 549   }
 550 }
 551
 552 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 553 {
 554   try {
 555     reg_t value = 0;
 556     memcpy(&value, bytes, len);
 557     set_csr(addr / (max_xlen / 8), value);
 558     return true;
 559   } catch (trap_illegal_instruction& t) {
 560     return false;
 561   }
 562 }