riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121 }
 122
 123 void processor_t::set_debug(bool value)
 124 {
 125   debug = value;
 126   if (ext)
 127     ext->set_debug(value);
 128 }
 129
 130 void processor_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133 #ifndef RISCV_ENABLE_HISTOGRAM
 134   if (value) {
 135     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 136     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 137   }
 138 #endif
 139 }
 140
 141 void processor_t::reset()
 142 {
 143   state.reset();
 144   state.dcsr.halt = halt_on_reset;
 145   halt_on_reset = false;
 146   set_csr(CSR_MSTATUS, state.mstatus);
 147
 148   if (ext)
 149     ext->reset(); // reset the extension
 150 }
 151
 152 void processor_t::raise_interrupt(reg_t which)
 153 {
 154   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 155 }
 156
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt()
 167 {
 168   reg_t pending_interrupts = state.mip & state.mie;
 169
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 177
 178   if (enabled_interrupts)
 179     raise_interrupt(ctz(enabled_interrupts));
 180 }
 181
 182 bool processor_t::validate_priv(reg_t priv)
 183 {
 184   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 185 }
 186
 187 void processor_t::set_privilege(reg_t prv)
 188 {
 189   assert(validate_priv(prv));
 190   mmu->flush_tlb();
 191   state.prv = prv;
 192 }
 193
 194 void processor_t::enter_debug_mode(uint8_t cause)
 195 {
 196   state.dcsr.cause = cause;
 197   state.dcsr.prv = state.prv;
 198   set_privilege(PRV_M);
 199   state.dpc = state.pc;
 200   state.pc = DEBUG_ROM_START;
 201   //debug = true; // TODO
 202 }
 203
 204 void processor_t::take_trap(trap_t& t, reg_t epc)
 205 {
 206   if (debug) {
 207     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 208             id, t.name(), epc);
 209     if (t.has_badaddr())
 210       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 211           t.get_badaddr());
 212   }
 213
 214   if (t.cause() == CAUSE_BREAKPOINT && (
 215               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 216               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 217               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 218               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 219     enter_debug_mode(DCSR_CAUSE_SWBP);
 220     return;
 221   }
 222
 223   if (state.dcsr.cause) {
 224     state.pc = DEBUG_ROM_EXCEPTION;
 225     return;
 226   }
 227
 228   // by default, trap to M-mode, unless delegated to S-mode
 229   reg_t bit = t.cause();
 230   reg_t deleg = state.medeleg;
 231   if (bit & ((reg_t)1 << (max_xlen-1)))
 232     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 233   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 234     // handle the trap in S-mode
 235     state.pc = state.stvec;
 236     state.scause = t.cause();
 237     state.sepc = epc;
 238     if (t.has_badaddr())
 239       state.sbadaddr = t.get_badaddr();
 240
 241     reg_t s = state.mstatus;
 242     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 243     s = set_field(s, MSTATUS_SPP, state.prv);
 244     s = set_field(s, MSTATUS_SIE, 0);
 245     set_csr(CSR_MSTATUS, s);
 246     set_privilege(PRV_S);
 247   } else {
 248     state.pc = state.mtvec;
 249     state.mepc = epc;
 250     state.mcause = t.cause();
 251     if (t.has_badaddr())
 252       state.mbadaddr = t.get_badaddr();
 253
 254     reg_t s = state.mstatus;
 255     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 256     s = set_field(s, MSTATUS_MPP, state.prv);
 257     s = set_field(s, MSTATUS_MIE, 0);
 258     set_csr(CSR_MSTATUS, s);
 259     set_privilege(PRV_M);
 260   }
 261
 262   yield_load_reservation();
 263 }
 264
 265 void processor_t::disasm(insn_t insn)
 266 {
 267   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 268   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 269           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 270 }
 271
 272 static bool validate_vm(int max_xlen, reg_t vm)
 273 {
 274   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 275     return true;
 276   if (max_xlen == 32 && vm == VM_SV32)
 277     return true;
 278   return vm == VM_MBARE;
 279 }
 280
 281 int processor_t::paddr_bits()
 282 {
 283   assert(xlen == max_xlen);
 284   return max_xlen == 64 ? 50 : 34;
 285 }
 286
 287 void processor_t::set_csr(int which, reg_t val)
 288 {
 289   val = zext_xlen(val);
 290   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 291   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 292   switch (which)
 293   {
 294     case CSR_FFLAGS:
 295       dirty_fp_state;
 296       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 297       break;
 298     case CSR_FRM:
 299       dirty_fp_state;
 300       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 301       break;
 302     case CSR_FCSR:
 303       dirty_fp_state;
 304       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 305       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 306       break;
 307     case CSR_MSTATUS: {
 308       if ((val ^ state.mstatus) &
 309           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 310         mmu->flush_tlb();
 311
 312       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 313                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 314                  | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 315
 316       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 317         mask |= MSTATUS_VM;
 318       if (validate_priv(get_field(val, MSTATUS_MPP)))
 319         mask |= MSTATUS_MPP;
 320
 321       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 322
 323       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 324       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 325       if (max_xlen == 32)
 326         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 327       else
 328         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 329
 330       // spike supports the notion of xlen < max_xlen, but current priv spec
 331       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 332       xlen = max_xlen;
 333       break;
 334     }
 335     case CSR_MIP: {
 336       reg_t mask = MIP_SSIP | MIP_STIP;
 337       state.mip = (state.mip & ~mask) | (val & mask);
 338       break;
 339     }
 340     case CSR_MIE:
 341       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 342       break;
 343     case CSR_MIDELEG:
 344       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 345       break;
 346     case CSR_MEDELEG: {
 347       reg_t mask = 0;
 348 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 349 #include "encoding.h"
 350 #undef DECLARE_CAUSE
 351       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 352       break;
 353     }
 354     case CSR_MUCOUNTEREN:
 355       state.mucounteren = val & 7;
 356       break;
 357     case CSR_MSCOUNTEREN:
 358       state.mscounteren = val & 7;
 359       break;
 360     case CSR_SSTATUS: {
 361       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 362                  | SSTATUS_XS | SSTATUS_PUM;
 363       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 364     }
 365     case CSR_SIP:
 366       return set_csr(CSR_MIP,
 367                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 368     case CSR_SIE:
 369       return set_csr(CSR_MIE,
 370                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 371     case CSR_SPTBR: {
 372       // upper bits of sptbr are the ASID; we only support ASID = 0
 373       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 374       break;
 375     }
 376     case CSR_SEPC: state.sepc = val; break;
 377     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 378     case CSR_SSCRATCH: state.sscratch = val; break;
 379     case CSR_SCAUSE: state.scause = val; break;
 380     case CSR_SBADADDR: state.sbadaddr = val; break;
 381     case CSR_MEPC: state.mepc = val; break;
 382     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 383     case CSR_MSCRATCH: state.mscratch = val; break;
 384     case CSR_MCAUSE: state.mcause = val; break;
 385     case CSR_MBADADDR: state.mbadaddr = val; break;
 386     case CSR_DCSR:
 387       state.dcsr.prv = get_field(val, DCSR_PRV);
 388       state.dcsr.step = get_field(val, DCSR_STEP);
 389       // TODO: ndreset and fullreset
 390       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 391       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 392       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 393       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 394       state.dcsr.halt = get_field(val, DCSR_HALT);
 395       break;
 396     case CSR_DPC:
 397       state.dpc = val;
 398       break;
 399     case CSR_DSCRATCH:
 400       state.dscratch = val;
 401       break;
 402   }
 403 }
 404
 405 reg_t processor_t::get_csr(int which)
 406 {
 407   switch (which)
 408   {
 409     case CSR_FFLAGS:
 410       require_fp;
 411       if (!supports_extension('F'))
 412         break;
 413       return state.fflags;
 414     case CSR_FRM:
 415       require_fp;
 416       if (!supports_extension('F'))
 417         break;
 418       return state.frm;
 419     case CSR_FCSR:
 420       require_fp;
 421       if (!supports_extension('F'))
 422         break;
 423       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 424     case CSR_TIME:
 425     case CSR_INSTRET:
 426     case CSR_CYCLE:
 427       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 428         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 429       break;
 430     case CSR_STIME:
 431     case CSR_SINSTRET:
 432     case CSR_SCYCLE:
 433       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 434         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 435       break;
 436     case CSR_MUCOUNTEREN: return state.mucounteren;
 437     case CSR_MSCOUNTEREN: return state.mscounteren;
 438     case CSR_MUCYCLE_DELTA: return 0;
 439     case CSR_MUTIME_DELTA: return 0;
 440     case CSR_MUINSTRET_DELTA: return 0;
 441     case CSR_MSCYCLE_DELTA: return 0;
 442     case CSR_MSTIME_DELTA: return 0;
 443     case CSR_MSINSTRET_DELTA: return 0;
 444     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 445     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 446     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 447     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 448     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 449     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 450     case CSR_MCYCLE: return state.minstret;
 451     case CSR_MINSTRET: return state.minstret;
 452     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 453     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 454     case CSR_SSTATUS: {
 455       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 456                  | SSTATUS_XS | SSTATUS_PUM;
 457       reg_t sstatus = state.mstatus & mask;
 458       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 459           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 460         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 461       return sstatus;
 462     }
 463     case CSR_SIP: return state.mip & state.mideleg;
 464     case CSR_SIE: return state.mie & state.mideleg;
 465     case CSR_SEPC: return state.sepc;
 466     case CSR_SBADADDR: return state.sbadaddr;
 467     case CSR_STVEC: return state.stvec;
 468     case CSR_SCAUSE:
 469       if (max_xlen > xlen)
 470         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 471       return state.scause;
 472     case CSR_SPTBR: return state.sptbr;
 473     case CSR_SSCRATCH: return state.sscratch;
 474     case CSR_MSTATUS: return state.mstatus;
 475     case CSR_MIP: return state.mip;
 476     case CSR_MIE: return state.mie;
 477     case CSR_MEPC: return state.mepc;
 478     case CSR_MSCRATCH: return state.mscratch;
 479     case CSR_MCAUSE: return state.mcause;
 480     case CSR_MBADADDR: return state.mbadaddr;
 481     case CSR_MISA: return isa;
 482     case CSR_MARCHID: return 0;
 483     case CSR_MIMPID: return 0;
 484     case CSR_MVENDORID: return 0;
 485     case CSR_MHARTID: return id;
 486     case CSR_MTVEC: return state.mtvec;
 487     case CSR_MEDELEG: return state.medeleg;
 488     case CSR_MIDELEG: return state.mideleg;
 489     case CSR_TDRSELECT: return 0;
 490     case CSR_DCSR:
 491       {
 492         uint32_t v = 0;
 493         v = set_field(v, DCSR_XDEBUGVER, 1);
 494         v = set_field(v, DCSR_HWBPCOUNT, 0);
 495         v = set_field(v, DCSR_NDRESET, 0);
 496         v = set_field(v, DCSR_FULLRESET, 0);
 497         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 498         v = set_field(v, DCSR_STEP, state.dcsr.step);
 499         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 500         v = set_field(v, DCSR_STOPCYCLE, 0);
 501         v = set_field(v, DCSR_STOPTIME, 0);
 502         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 503         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 504         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 505         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 506         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 507         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 508         return v;
 509       }
 510     case CSR_DPC:
 511       return state.dpc;
 512     case CSR_DSCRATCH:
 513       return state.dscratch;
 514   }
 515   throw trap_illegal_instruction();
 516 }
 517
 518 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 519 {
 520   throw trap_illegal_instruction();
 521 }
 522
 523 insn_func_t processor_t::decode_insn(insn_t insn)
 524 {
 525   // look up opcode in hash table
 526   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 527   insn_desc_t desc = opcode_cache[idx];
 528
 529   if (unlikely(insn.bits() != desc.match)) {
 530     // fall back to linear search
 531     insn_desc_t* p = &instructions[0];
 532     while ((insn.bits() & p->mask) != p->match)
 533       p++;
 534     desc = *p;
 535
 536     if (p->mask != 0 && p > &instructions[0]) {
 537       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 538         // move to front of opcode list to reduce miss penalty
 539         while (--p >= &instructions[0])
 540           *(p+1) = *p;
 541         instructions[0] = desc;
 542       }
 543     }
 544
 545     opcode_cache[idx] = desc;
 546     opcode_cache[idx].match = insn.bits();
 547   }
 548
 549   return xlen == 64 ? desc.rv64 : desc.rv32;
 550 }
 551
 552 void processor_t::register_insn(insn_desc_t desc)
 553 {
 554   instructions.push_back(desc);
 555 }
 556
 557 void processor_t::build_opcode_map()
 558 {
 559   struct cmp {
 560     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 561       if (lhs.match == rhs.match)
 562         return lhs.mask > rhs.mask;
 563       return lhs.match > rhs.match;
 564     }
 565   };
 566   std::sort(instructions.begin(), instructions.end(), cmp());
 567
 568   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 569     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 570 }
 571
 572 void processor_t::register_extension(extension_t* x)
 573 {
 574   for (auto insn : x->get_instructions())
 575     register_insn(insn);
 576   build_opcode_map();
 577   for (auto disasm_insn : x->get_disasms())
 578     disassembler->add_insn(disasm_insn);
 579   if (ext != NULL)
 580     throw std::logic_error("only one extension may be registered");
 581   ext = x;
 582   x->set_processor(this);
 583 }
 584
 585 void processor_t::register_base_instructions()
 586 {
 587   #define DECLARE_INSN(name, match, mask) \
 588     insn_bits_t name##_match = (match), name##_mask = (mask);
 589   #include "encoding.h"
 590   #undef DECLARE_INSN
 591
 592   #define DEFINE_INSN(name) \
 593     REGISTER_INSN(this, name, name##_match, name##_mask)
 594   #include "insn_list.h"
 595   #undef DEFINE_INSN
 596
 597   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 598   build_opcode_map();
 599 }
 600
 601 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 602 {
 603   return false;
 604 }
 605
 606 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 607 {
 608   switch (addr)
 609   {
 610     case 0:
 611       state.mip &= ~MIP_MSIP;
 612       if (bytes[0] & 1)
 613         state.mip |= MIP_MSIP;
 614       return true;
 615
 616     default:
 617       return false;
 618   }
 619 }