riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = 0, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // if we have IMAFD, advertise G, too
 109   if (supports_extension('I') && supports_extension('M') &&
 110       supports_extension('A') && supports_extension('D'))
 111     isa |= 1L << ('g' - 'a');
 112
 113   // advertise support for supervisor and user modes
 114   isa |= 1L << ('s' - 'a');
 115   isa |= 1L << ('u' - 'a');
 116 }
 117
 118 void state_t::reset()
 119 {
 120   memset(this, 0, sizeof(*this));
 121   prv = PRV_M;
 122   pc = DEFAULT_RSTVEC;
 123   load_reservation = -1;
 124 }
 125
 126 void processor_t::set_debug(bool value)
 127 {
 128   debug = value;
 129   if (ext)
 130     ext->set_debug(value);
 131 }
 132
 133 void processor_t::set_histogram(bool value)
 134 {
 135   histogram_enabled = value;
 136 #ifndef RISCV_ENABLE_HISTOGRAM
 137   if (value) {
 138     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 139     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 140   }
 141 #endif
 142 }
 143
 144 void processor_t::reset(bool value)
 145 {
 146   if (run == !value)
 147     return;
 148   run = !value;
 149
 150   state.reset();
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 void processor_t::raise_interrupt(reg_t which)
 158 {
 159   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 160 }
 161
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt()
 172 {
 173   check_timer();
 174
 175   reg_t interrupts = state.mip & state.mie;
 176
 177   reg_t m_interrupts = interrupts & ~state.mideleg;
 178   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 179   if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
 180     raise_interrupt(ctz(m_interrupts));
 181
 182   reg_t s_interrupts = interrupts & state.mideleg;
 183   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 184   if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
 185     raise_interrupt(ctz(s_interrupts));
 186 }
 187
 188 void processor_t::check_timer()
 189 {
 190   if (sim->rtc >= state.mtimecmp)
 191     state.mip |= MIP_MTIP;
 192 }
 193
 194 static bool validate_priv(reg_t priv)
 195 {
 196   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 197 }
 198
 199 void processor_t::set_privilege(reg_t prv)
 200 {
 201   assert(validate_priv(prv));
 202   mmu->flush_tlb();
 203   state.prv = prv;
 204 }
 205
 206 void processor_t::take_trap(trap_t& t, reg_t epc)
 207 {
 208   if (debug)
 209     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 210             id, t.name(), epc);
 211
 212   // by default, trap to M-mode, unless delegated to S-mode
 213   reg_t bit = t.cause();
 214   reg_t deleg = state.medeleg;
 215   if (bit & ((reg_t)1 << (max_xlen-1)))
 216     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 217   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 218     // handle the trap in S-mode
 219     state.pc = state.stvec;
 220     state.scause = t.cause();
 221     state.sepc = epc;
 222     if (t.has_badaddr())
 223       state.sbadaddr = t.get_badaddr();
 224
 225     reg_t s = state.mstatus;
 226     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 227     s = set_field(s, MSTATUS_SPP, state.prv);
 228     s = set_field(s, MSTATUS_SIE, 0);
 229     set_csr(CSR_MSTATUS, s);
 230     set_privilege(PRV_S);
 231   } else {
 232     state.pc = DEFAULT_MTVEC;
 233     state.mcause = t.cause();
 234     state.mepc = epc;
 235     if (t.has_badaddr())
 236       state.mbadaddr = t.get_badaddr();
 237
 238     reg_t s = state.mstatus;
 239     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 240     s = set_field(s, MSTATUS_MPP, state.prv);
 241     s = set_field(s, MSTATUS_MIE, 0);
 242     set_csr(CSR_MSTATUS, s);
 243     set_privilege(PRV_M);
 244   }
 245
 246   yield_load_reservation();
 247 }
 248
 249 void processor_t::disasm(insn_t insn)
 250 {
 251   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 252   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 253           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 254 }
 255
 256 static bool validate_vm(int max_xlen, reg_t vm)
 257 {
 258   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 259     return true;
 260   if (max_xlen == 32 && vm == VM_SV32)
 261     return true;
 262   return vm == VM_MBARE;
 263 }
 264
 265 void processor_t::set_csr(int which, reg_t val)
 266 {
 267   val = zext_xlen(val);
 268   reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
 269   reg_t s_ints = MIP_SSIP | MIP_STIP;
 270   switch (which)
 271   {
 272     case CSR_FFLAGS:
 273       dirty_fp_state;
 274       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 275       break;
 276     case CSR_FRM:
 277       dirty_fp_state;
 278       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 279       break;
 280     case CSR_FCSR:
 281       dirty_fp_state;
 282       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 283       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 284       break;
 285     case CSR_MSTATUS: {
 286       if ((val ^ state.mstatus) &
 287           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 288         mmu->flush_tlb();
 289
 290       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 291                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 292                  | (ext ? MSTATUS_XS : 0);
 293
 294       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 295         mask |= MSTATUS_VM;
 296       if (validate_priv(get_field(val, MSTATUS_MPP)))
 297         mask |= MSTATUS_MPP;
 298
 299       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 300
 301       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 302       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 303       if (max_xlen == 32)
 304         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 305       else
 306         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 307
 308       // spike supports the notion of xlen < max_xlen, but current priv spec
 309       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 310       xlen = max_xlen;
 311       break;
 312     }
 313     case CSR_MIP: {
 314       reg_t mask = all_ints &~ MIP_MTIP;
 315       state.mip = (state.mip & ~mask) | (val & mask);
 316       break;
 317     }
 318     case CSR_MIPI:
 319       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 320       break;
 321     case CSR_MIE:
 322       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 323       break;
 324     case CSR_MIDELEG:
 325       state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
 326       break;
 327     case CSR_MEDELEG: {
 328       reg_t mask = 0;
 329 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 330 #include "encoding.h"
 331 #undef DECLARE_CAUSE
 332       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 333       break;
 334     }
 335     case CSR_SSTATUS: {
 336       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 337                  | SSTATUS_XS | SSTATUS_PUM;
 338       set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 339       break;
 340     }
 341     case CSR_SIP: {
 342       reg_t mask = s_ints &~ MIP_STIP;
 343       state.mip = (state.mip & ~mask) | (val & mask);
 344       break;
 345     }
 346     case CSR_SIE: {
 347       reg_t mask = s_ints;
 348       state.mie = (state.mie & ~mask) | (val & mask);
 349       break;
 350     }
 351     case CSR_SEPC: state.sepc = val; break;
 352     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 353     case CSR_SPTBR: state.sptbr = val; break;
 354     case CSR_SSCRATCH: state.sscratch = val; break;
 355     case CSR_SCAUSE: state.scause = val; break;
 356     case CSR_SBADADDR: state.sbadaddr = val; break;
 357     case CSR_MEPC: state.mepc = val; break;
 358     case CSR_MSCRATCH: state.mscratch = val; break;
 359     case CSR_MCAUSE: state.mcause = val; break;
 360     case CSR_MBADADDR: state.mbadaddr = val; break;
 361     case CSR_MTIMECMP:
 362       state.mip &= ~MIP_MTIP;
 363       state.mtimecmp = val;
 364       break;
 365     case CSR_MTOHOST:
 366       if (state.tohost == 0)
 367         state.tohost = val;
 368       break;
 369     case CSR_MFROMHOST:
 370       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 371       state.fromhost = val;
 372       break;
 373   }
 374 }
 375
 376 reg_t processor_t::get_csr(int which)
 377 {
 378   switch (which)
 379   {
 380     case CSR_FFLAGS:
 381       require_fp;
 382       if (!supports_extension('F'))
 383         break;
 384       return state.fflags;
 385     case CSR_FRM:
 386       require_fp;
 387       if (!supports_extension('F'))
 388         break;
 389       return state.frm;
 390     case CSR_FCSR:
 391       require_fp;
 392       if (!supports_extension('F'))
 393         break;
 394       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 395     case CSR_MTIME: return sim->rtc;
 396     case CSR_MCYCLE: return state.minstret;
 397     case CSR_MINSTRET: return state.minstret;
 398     case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32;
 399     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 400     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 401     case CSR_SSTATUS: {
 402       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 403                  | SSTATUS_XS | SSTATUS_PUM;
 404       reg_t sstatus = state.mstatus & mask;
 405       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 406           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 407         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 408       return sstatus;
 409     }
 410     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 411     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 412     case CSR_SEPC: return state.sepc;
 413     case CSR_SBADADDR: return state.sbadaddr;
 414     case CSR_STVEC: return state.stvec;
 415     case CSR_SCAUSE:
 416       if (max_xlen > xlen)
 417         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 418       return state.scause;
 419     case CSR_SPTBR: return state.sptbr;
 420     case CSR_SASID: return 0;
 421     case CSR_SSCRATCH: return state.sscratch;
 422     case CSR_MSTATUS: return state.mstatus;
 423     case CSR_MIP: return state.mip;
 424     case CSR_MIPI: return 0;
 425     case CSR_MIE: return state.mie;
 426     case CSR_MEPC: return state.mepc;
 427     case CSR_MSCRATCH: return state.mscratch;
 428     case CSR_MCAUSE: return state.mcause;
 429     case CSR_MBADADDR: return state.mbadaddr;
 430     case CSR_MTIMECMP: return state.mtimecmp;
 431     case CSR_MISA: return isa;
 432     case CSR_MARCHID: return 0;
 433     case CSR_MIMPID: return 0;
 434     case CSR_MVENDORID: return 0;
 435     case CSR_MHARTID: return id;
 436     case CSR_MTVEC: return DEFAULT_MTVEC;
 437     case CSR_MEDELEG: return state.medeleg;
 438     case CSR_MIDELEG: return state.mideleg;
 439     case CSR_MTOHOST:
 440       sim->get_htif()->tick(); // not necessary, but faster
 441       return state.tohost;
 442     case CSR_MFROMHOST:
 443       sim->get_htif()->tick(); // not necessary, but faster
 444       return state.fromhost;
 445     case CSR_MCFGADDR: return sim->memsz;
 446     case CSR_UARCH0:
 447     case CSR_UARCH1:
 448     case CSR_UARCH2:
 449     case CSR_UARCH3:
 450     case CSR_UARCH4:
 451     case CSR_UARCH5:
 452     case CSR_UARCH6:
 453     case CSR_UARCH7:
 454     case CSR_UARCH8:
 455     case CSR_UARCH9:
 456     case CSR_UARCH10:
 457     case CSR_UARCH11:
 458     case CSR_UARCH12:
 459     case CSR_UARCH13:
 460     case CSR_UARCH14:
 461     case CSR_UARCH15:
 462       return 0;
 463   }
 464   throw trap_illegal_instruction();
 465 }
 466
 467 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 468 {
 469   throw trap_illegal_instruction();
 470 }
 471
 472 insn_func_t processor_t::decode_insn(insn_t insn)
 473 {
 474   // look up opcode in hash table
 475   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 476   insn_desc_t desc = opcode_cache[idx];
 477
 478   if (unlikely(insn.bits() != desc.match)) {
 479     // fall back to linear search
 480     insn_desc_t* p = &instructions[0];
 481     while ((insn.bits() & p->mask) != p->match)
 482       p++;
 483     desc = *p;
 484
 485     if (p->mask != 0 && p > &instructions[0]) {
 486       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 487         // move to front of opcode list to reduce miss penalty
 488         while (--p >= &instructions[0])
 489           *(p+1) = *p;
 490         instructions[0] = desc;
 491       }
 492     }
 493
 494     opcode_cache[idx] = desc;
 495     opcode_cache[idx].match = insn.bits();
 496   }
 497
 498   return xlen == 64 ? desc.rv64 : desc.rv32;
 499 }
 500
 501 void processor_t::register_insn(insn_desc_t desc)
 502 {
 503   instructions.push_back(desc);
 504 }
 505
 506 void processor_t::build_opcode_map()
 507 {
 508   struct cmp {
 509     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 510       if (lhs.match == rhs.match)
 511         return lhs.mask > rhs.mask;
 512       return lhs.match > rhs.match;
 513     }
 514   };
 515   std::sort(instructions.begin(), instructions.end(), cmp());
 516
 517   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 518     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 519 }
 520
 521 void processor_t::register_extension(extension_t* x)
 522 {
 523   for (auto insn : x->get_instructions())
 524     register_insn(insn);
 525   build_opcode_map();
 526   for (auto disasm_insn : x->get_disasms())
 527     disassembler->add_insn(disasm_insn);
 528   if (ext != NULL)
 529     throw std::logic_error("only one extension may be registered");
 530   ext = x;
 531   x->set_processor(this);
 532 }
 533
 534 void processor_t::register_base_instructions()
 535 {
 536   #define DECLARE_INSN(name, match, mask) \
 537     insn_bits_t name##_match = (match), name##_mask = (mask);
 538   #include "encoding.h"
 539   #undef DECLARE_INSN
 540
 541   #define DEFINE_INSN(name) \
 542     REGISTER_INSN(this, name, name##_match, name##_mask)
 543   #include "insn_list.h"
 544   #undef DEFINE_INSN
 545
 546   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 547   build_opcode_map();
 548 }
 549
 550 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 551 {
 552   try {
 553     auto res = get_csr(addr / (max_xlen / 8));
 554     memcpy(bytes, &res, len);
 555     return true;
 556   } catch (trap_illegal_instruction& t) {
 557     return false;
 558   }
 559 }
 560
 561 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 562 {
 563   try {
 564     reg_t value = 0;
 565     memcpy(&value, bytes, len);
 566     set_csr(addr / (max_xlen / 8), value);
 567     return true;
 568   } catch (trap_illegal_instruction& t) {
 569     return false;
 570   }
 571 }