riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include "gdbserver.h"
  12 #include <cinttypes>
  13 #include <cmath>
  14 #include <cstdlib>
  15 #include <iostream>
  16 #include <assert.h>
  17 #include <limits.h>
  18 #include <stdexcept>
  19 #include <algorithm>
  20
  21 #undef STATE
  22 #define STATE state
  23
  24 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  25         bool halt_on_reset)
  26   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
  27     id(id), run(false), halt_on_reset(halt_on_reset)
  28 {
  29   parse_isa_string(isa);
  30
  31   mmu = new mmu_t(sim, this);
  32
  33   reset(true);
  34
  35   register_base_instructions();
  36 }
  37
  38 processor_t::~processor_t()
  39 {
  40 #ifdef RISCV_ENABLE_HISTOGRAM
  41   if (histogram_enabled)
  42   {
  43     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  44     for (auto it : pc_histogram)
  45       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  46   }
  47 #endif
  48
  49   delete mmu;
  50   delete disassembler;
  51 }
  52
  53 static void bad_isa_string(const char* isa)
  54 {
  55   fprintf(stderr, "error: bad --isa option %s\n", isa);
  56   abort();
  57 }
  58
  59 void processor_t::parse_isa_string(const char* str)
  60 {
  61   std::string lowercase, tmp;
  62   for (const char *r = str; *r; r++)
  63     lowercase += std::tolower(*r);
  64
  65   const char* p = lowercase.c_str();
  66   const char* all_subsets = "imafdc";
  67
  68   max_xlen = 64;
  69   isa = reg_t(2) << 62;
  70
  71   if (strncmp(p, "rv32", 4) == 0)
  72     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  73   else if (strncmp(p, "rv64", 4) == 0)
  74     p += 4;
  75   else if (strncmp(p, "rv", 2) == 0)
  76     p += 2;
  77
  78   if (!*p) {
  79     p = all_subsets;
  80   } else if (*p == 'g') { // treat "G" as "IMAFD"
  81     tmp = std::string("imafd") + (p+1);
  82     p = &tmp[0];
  83   } else if (*p != 'i') {
  84     bad_isa_string(str);
  85   }
  86
  87   isa_string = "rv" + std::to_string(max_xlen) + p;
  88   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  89
  90   while (*p) {
  91     isa |= 1L << (*p - 'a');
  92
  93     if (auto next = strchr(all_subsets, *p)) {
  94       all_subsets = next + 1;
  95       p++;
  96     } else if (*p == 'x') {
  97       const char* ext = p+1, *end = ext;
  98       while (islower(*end))
  99         end++;
 100       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 101       p = end;
 102     } else {
 103       bad_isa_string(str);
 104     }
 105   }
 106
 107   if (supports_extension('D') && !supports_extension('F'))
 108     bad_isa_string(str);
 109
 110   // advertise support for supervisor and user modes
 111   isa |= 1L << ('s' - 'a');
 112   isa |= 1L << ('u' - 'a');
 113 }
 114
 115 void state_t::reset()
 116 {
 117   memset(this, 0, sizeof(*this));
 118   prv = PRV_M;
 119   pc = DEFAULT_RSTVEC;
 120   mtvec = DEFAULT_MTVEC;
 121   load_reservation = -1;
 122 }
 123
 124 void processor_t::set_debug(bool value)
 125 {
 126   debug = value;
 127   if (ext)
 128     ext->set_debug(value);
 129 }
 130
 131 void processor_t::set_histogram(bool value)
 132 {
 133   histogram_enabled = value;
 134 #ifndef RISCV_ENABLE_HISTOGRAM
 135   if (value) {
 136     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 137     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 138   }
 139 #endif
 140 }
 141
 142 void processor_t::reset(bool value)
 143 {
 144   if (run == !value)
 145     return;
 146   run = !value;
 147
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 void processor_t::raise_interrupt(reg_t which)
 158 {
 159   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 160 }
 161
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt()
 172 {
 173   reg_t pending_interrupts = state.mip & state.mie;
 174
 175   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 176   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 177   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 178
 179   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 180   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 181   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (enabled_interrupts)
 184     raise_interrupt(ctz(enabled_interrupts));
 185 }
 186
 187 static bool validate_priv(reg_t priv)
 188 {
 189   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 190 }
 191
 192 void processor_t::set_privilege(reg_t prv)
 193 {
 194   assert(validate_priv(prv));
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv);
 202   state.dcsr.cause = cause;
 203   state.dcsr.prv = state.prv;
 204   set_privilege(PRV_M);
 205   state.dpc = state.pc;
 206   state.pc = DEBUG_ROM_START;
 207   debug = true; // TODO
 208 }
 209
 210 void processor_t::take_trap(trap_t& t, reg_t epc)
 211 {
 212   if (debug) {
 213     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 214             id, t.name(), epc);
 215     if (t.has_badaddr())
 216       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 217           t.get_badaddr());
 218   }
 219
 220   if (t.cause() == CAUSE_BREAKPOINT && (
 221               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 222               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 223               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 224               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 225     enter_debug_mode(DCSR_CAUSE_SWBP);
 226     return;
 227   }
 228
 229   // by default, trap to M-mode, unless delegated to S-mode
 230   reg_t bit = t.cause();
 231   reg_t deleg = state.medeleg;
 232   if (bit & ((reg_t)1 << (max_xlen-1)))
 233     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 234   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 235     // handle the trap in S-mode
 236     state.pc = state.stvec;
 237     state.scause = t.cause();
 238     state.sepc = epc;
 239     if (t.has_badaddr())
 240       state.sbadaddr = t.get_badaddr();
 241
 242     reg_t s = state.mstatus;
 243     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 244     s = set_field(s, MSTATUS_SPP, state.prv);
 245     s = set_field(s, MSTATUS_SIE, 0);
 246     set_csr(CSR_MSTATUS, s);
 247     set_privilege(PRV_S);
 248   } else {
 249     if (state.dcsr.cause) {
 250       state.pc = DEBUG_ROM_EXCEPTION;
 251       state.dpc = epc;
 252     } else {
 253       state.pc = state.mtvec;
 254       state.mepc = epc;
 255     }
 256     state.mcause = t.cause();
 257     if (t.has_badaddr())
 258       state.mbadaddr = t.get_badaddr();
 259
 260     reg_t s = state.mstatus;
 261     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 262     s = set_field(s, MSTATUS_MPP, state.prv);
 263     s = set_field(s, MSTATUS_MIE, 0);
 264     set_csr(CSR_MSTATUS, s);
 265     set_privilege(PRV_M);
 266   }
 267
 268   yield_load_reservation();
 269 }
 270
 271 void processor_t::disasm(insn_t insn)
 272 {
 273   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 274   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 275           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 276 }
 277
 278 static bool validate_vm(int max_xlen, reg_t vm)
 279 {
 280   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 281     return true;
 282   if (max_xlen == 32 && vm == VM_SV32)
 283     return true;
 284   return vm == VM_MBARE;
 285 }
 286
 287 void processor_t::set_csr(int which, reg_t val)
 288 {
 289   val = zext_xlen(val);
 290   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 291   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 292   switch (which)
 293   {
 294     case CSR_FFLAGS:
 295       dirty_fp_state;
 296       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 297       break;
 298     case CSR_FRM:
 299       dirty_fp_state;
 300       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 301       break;
 302     case CSR_FCSR:
 303       dirty_fp_state;
 304       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 305       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 306       break;
 307     case CSR_MSTATUS: {
 308       if ((val ^ state.mstatus) &
 309           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 310         mmu->flush_tlb();
 311
 312       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 313                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 314                  | (ext ? MSTATUS_XS : 0);
 315
 316       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 317         mask |= MSTATUS_VM;
 318       if (validate_priv(get_field(val, MSTATUS_MPP)))
 319         mask |= MSTATUS_MPP;
 320
 321       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 322
 323       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 324       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 325       if (max_xlen == 32)
 326         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 327       else
 328         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 329
 330       // spike supports the notion of xlen < max_xlen, but current priv spec
 331       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 332       xlen = max_xlen;
 333       break;
 334     }
 335     case CSR_MIP: {
 336       reg_t mask = MIP_SSIP | MIP_STIP;
 337       state.mip = (state.mip & ~mask) | (val & mask);
 338       break;
 339     }
 340     case CSR_MIE:
 341       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 342       break;
 343     case CSR_MIDELEG:
 344       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 345       break;
 346     case CSR_MEDELEG: {
 347       reg_t mask = 0;
 348 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 349 #include "encoding.h"
 350 #undef DECLARE_CAUSE
 351       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 352       break;
 353     }
 354     case CSR_MUCOUNTEREN:
 355       state.mucounteren = val & 7;
 356       break;
 357     case CSR_MSCOUNTEREN:
 358       state.mscounteren = val & 7;
 359       break;
 360     case CSR_SSTATUS: {
 361       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 362                  | SSTATUS_XS | SSTATUS_PUM;
 363       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 364     }
 365     case CSR_SIP:
 366       return set_csr(CSR_MIP,
 367                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 368     case CSR_SIE:
 369       return set_csr(CSR_MIE,
 370                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 371     case CSR_SEPC: state.sepc = val; break;
 372     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 373     case CSR_SPTBR: state.sptbr = val; break;
 374     case CSR_SSCRATCH: state.sscratch = val; break;
 375     case CSR_SCAUSE: state.scause = val; break;
 376     case CSR_SBADADDR: state.sbadaddr = val; break;
 377     case CSR_MEPC: state.mepc = val; break;
 378     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 379     case CSR_MSCRATCH: state.mscratch = val; break;
 380     case CSR_MCAUSE: state.mcause = val; break;
 381     case CSR_MBADADDR: state.mbadaddr = val; break;
 382     case CSR_DCSR:
 383       state.dcsr.prv = get_field(val, DCSR_PRV);
 384       state.dcsr.step = get_field(val, DCSR_STEP);
 385       // TODO: ndreset and fullreset
 386       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 387       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 388       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 389       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 390       state.dcsr.halt = get_field(val, DCSR_HALT);
 391       break;
 392     case CSR_DPC:
 393       state.dpc = val;
 394       break;
 395     case CSR_DSCRATCH:
 396       state.dscratch = val;
 397       break;
 398   }
 399 }
 400
 401 reg_t processor_t::get_csr(int which)
 402 {
 403   switch (which)
 404   {
 405     case CSR_FFLAGS:
 406       require_fp;
 407       if (!supports_extension('F'))
 408         break;
 409       return state.fflags;
 410     case CSR_FRM:
 411       require_fp;
 412       if (!supports_extension('F'))
 413         break;
 414       return state.frm;
 415     case CSR_FCSR:
 416       require_fp;
 417       if (!supports_extension('F'))
 418         break;
 419       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 420     case CSR_TIME:
 421     case CSR_INSTRET:
 422     case CSR_CYCLE:
 423       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 424         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 425       break;
 426     case CSR_STIME:
 427     case CSR_SINSTRET:
 428     case CSR_SCYCLE:
 429       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 430         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 431       break;
 432     case CSR_MUCOUNTEREN: return state.mucounteren;
 433     case CSR_MSCOUNTEREN: return state.mscounteren;
 434     case CSR_MUCYCLE_DELTA: return 0;
 435     case CSR_MUTIME_DELTA: return 0;
 436     case CSR_MUINSTRET_DELTA: return 0;
 437     case CSR_MSCYCLE_DELTA: return 0;
 438     case CSR_MSTIME_DELTA: return 0;
 439     case CSR_MSINSTRET_DELTA: return 0;
 440     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 441     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 442     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 443     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 444     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 445     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 446     case CSR_MCYCLE: return state.minstret;
 447     case CSR_MINSTRET: return state.minstret;
 448     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 449     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 450     case CSR_SSTATUS: {
 451       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 452                  | SSTATUS_XS | SSTATUS_PUM;
 453       reg_t sstatus = state.mstatus & mask;
 454       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 455           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 456         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 457       return sstatus;
 458     }
 459     case CSR_SIP: return state.mip & state.mideleg;
 460     case CSR_SIE: return state.mie & state.mideleg;
 461     case CSR_SEPC: return state.sepc;
 462     case CSR_SBADADDR: return state.sbadaddr;
 463     case CSR_STVEC: return state.stvec;
 464     case CSR_SCAUSE:
 465       if (max_xlen > xlen)
 466         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 467       return state.scause;
 468     case CSR_SPTBR: return state.sptbr;
 469     case CSR_SASID: return 0;
 470     case CSR_SSCRATCH: return state.sscratch;
 471     case CSR_MSTATUS: return state.mstatus;
 472     case CSR_MIP: return state.mip;
 473     case CSR_MIE: return state.mie;
 474     case CSR_MEPC: return state.mepc;
 475     case CSR_MSCRATCH: return state.mscratch;
 476     case CSR_MCAUSE: return state.mcause;
 477     case CSR_MBADADDR: return state.mbadaddr;
 478     case CSR_MISA: return isa;
 479     case CSR_MARCHID: return 0;
 480     case CSR_MIMPID: return 0;
 481     case CSR_MVENDORID: return 0;
 482     case CSR_MHARTID: return id;
 483     case CSR_MTVEC: return state.mtvec;
 484     case CSR_MEDELEG: return state.medeleg;
 485     case CSR_MIDELEG: return state.mideleg;
 486     case CSR_DCSR:
 487       {
 488         uint32_t v = 0;
 489         v = set_field(v, DCSR_XDEBUGVER, 1);
 490         v = set_field(v, DCSR_HWBPCOUNT, 0);
 491         v = set_field(v, DCSR_NDRESET, 0);
 492         v = set_field(v, DCSR_FULLRESET, 0);
 493         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 494         v = set_field(v, DCSR_STEP, state.dcsr.step);
 495         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 496         v = set_field(v, DCSR_STOPCYCLE, 0);
 497         v = set_field(v, DCSR_STOPTIME, 0);
 498         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 499         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 500         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 501         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 502         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 503         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 504         return v;
 505       }
 506     case CSR_DPC:
 507       return state.dpc;
 508     case CSR_DSCRATCH:
 509       return state.dscratch;
 510   }
 511   throw trap_illegal_instruction();
 512 }
 513
 514 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 515 {
 516   throw trap_illegal_instruction();
 517 }
 518
 519 insn_func_t processor_t::decode_insn(insn_t insn)
 520 {
 521   // look up opcode in hash table
 522   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 523   insn_desc_t desc = opcode_cache[idx];
 524
 525   if (unlikely(insn.bits() != desc.match)) {
 526     // fall back to linear search
 527     insn_desc_t* p = &instructions[0];
 528     while ((insn.bits() & p->mask) != p->match)
 529       p++;
 530     desc = *p;
 531
 532     if (p->mask != 0 && p > &instructions[0]) {
 533       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 534         // move to front of opcode list to reduce miss penalty
 535         while (--p >= &instructions[0])
 536           *(p+1) = *p;
 537         instructions[0] = desc;
 538       }
 539     }
 540
 541     opcode_cache[idx] = desc;
 542     opcode_cache[idx].match = insn.bits();
 543   }
 544
 545   return xlen == 64 ? desc.rv64 : desc.rv32;
 546 }
 547
 548 void processor_t::register_insn(insn_desc_t desc)
 549 {
 550   instructions.push_back(desc);
 551 }
 552
 553 void processor_t::build_opcode_map()
 554 {
 555   struct cmp {
 556     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 557       if (lhs.match == rhs.match)
 558         return lhs.mask > rhs.mask;
 559       return lhs.match > rhs.match;
 560     }
 561   };
 562   std::sort(instructions.begin(), instructions.end(), cmp());
 563
 564   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 565     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 566 }
 567
 568 void processor_t::register_extension(extension_t* x)
 569 {
 570   for (auto insn : x->get_instructions())
 571     register_insn(insn);
 572   build_opcode_map();
 573   for (auto disasm_insn : x->get_disasms())
 574     disassembler->add_insn(disasm_insn);
 575   if (ext != NULL)
 576     throw std::logic_error("only one extension may be registered");
 577   ext = x;
 578   x->set_processor(this);
 579 }
 580
 581 void processor_t::register_base_instructions()
 582 {
 583   #define DECLARE_INSN(name, match, mask) \
 584     insn_bits_t name##_match = (match), name##_mask = (mask);
 585   #include "encoding.h"
 586   #undef DECLARE_INSN
 587
 588   #define DEFINE_INSN(name) \
 589     REGISTER_INSN(this, name, name##_match, name##_mask)
 590   #include "insn_list.h"
 591   #undef DEFINE_INSN
 592
 593   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 594   build_opcode_map();
 595 }
 596
 597 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 598 {
 599   return false;
 600 }
 601
 602 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 603 {
 604   switch (addr)
 605   {
 606     case 0:
 607       state.mip &= ~MIP_MSIP;
 608       if (bytes[0] & 1)
 609         state.mip |= MIP_MSIP;
 610       return true;
 611
 612     default:
 613       return false;
 614   }
 615 }