riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121 }
 122
 123 void processor_t::set_debug(bool value)
 124 {
 125   debug = value;
 126   if (ext)
 127     ext->set_debug(value);
 128 }
 129
 130 void processor_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133 #ifndef RISCV_ENABLE_HISTOGRAM
 134   if (value) {
 135     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 136     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 137   }
 138 #endif
 139 }
 140
 141 void processor_t::reset()
 142 {
 143   state.reset();
 144   state.dcsr.halt = halt_on_reset;
 145   halt_on_reset = false;
 146   set_csr(CSR_MSTATUS, state.mstatus);
 147
 148   if (ext)
 149     ext->reset(); // reset the extension
 150 }
 151
 152 void processor_t::raise_interrupt(reg_t which)
 153 {
 154   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 155 }
 156
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt()
 167 {
 168   reg_t pending_interrupts = state.mip & state.mie;
 169
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 177
 178   if (enabled_interrupts)
 179     raise_interrupt(ctz(enabled_interrupts));
 180 }
 181
 182 void processor_t::set_privilege(reg_t prv)
 183 {
 184   assert(prv <= PRV_M);
 185   if (prv == PRV_H)
 186     prv = PRV_U;
 187   mmu->flush_tlb();
 188   state.prv = prv;
 189 }
 190
 191 void processor_t::enter_debug_mode(uint8_t cause)
 192 {
 193   state.dcsr.cause = cause;
 194   state.dcsr.prv = state.prv;
 195   set_privilege(PRV_M);
 196   state.dpc = state.pc;
 197   state.pc = DEBUG_ROM_START;
 198   //debug = true; // TODO
 199 }
 200
 201 void processor_t::take_trap(trap_t& t, reg_t epc)
 202 {
 203   if (debug) {
 204     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 205             id, t.name(), epc);
 206     if (t.has_badaddr())
 207       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 208           t.get_badaddr());
 209   }
 210
 211   if (t.cause() == CAUSE_BREAKPOINT && (
 212               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 213               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 214               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 215               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 216     enter_debug_mode(DCSR_CAUSE_SWBP);
 217     return;
 218   }
 219
 220   if (state.dcsr.cause) {
 221     state.pc = DEBUG_ROM_EXCEPTION;
 222     return;
 223   }
 224
 225   // by default, trap to M-mode, unless delegated to S-mode
 226   reg_t bit = t.cause();
 227   reg_t deleg = state.medeleg;
 228   if (bit & ((reg_t)1 << (max_xlen-1)))
 229     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 230   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 231     // handle the trap in S-mode
 232     state.pc = state.stvec;
 233     state.scause = t.cause();
 234     state.sepc = epc;
 235     if (t.has_badaddr())
 236       state.sbadaddr = t.get_badaddr();
 237
 238     reg_t s = state.mstatus;
 239     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 240     s = set_field(s, MSTATUS_SPP, state.prv);
 241     s = set_field(s, MSTATUS_SIE, 0);
 242     set_csr(CSR_MSTATUS, s);
 243     set_privilege(PRV_S);
 244   } else {
 245     state.pc = state.mtvec;
 246     state.mepc = epc;
 247     state.mcause = t.cause();
 248     if (t.has_badaddr())
 249       state.mbadaddr = t.get_badaddr();
 250
 251     reg_t s = state.mstatus;
 252     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 253     s = set_field(s, MSTATUS_MPP, state.prv);
 254     s = set_field(s, MSTATUS_MIE, 0);
 255     set_csr(CSR_MSTATUS, s);
 256     set_privilege(PRV_M);
 257   }
 258
 259   yield_load_reservation();
 260 }
 261
 262 void processor_t::disasm(insn_t insn)
 263 {
 264   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 265   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 266           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 267 }
 268
 269 static bool validate_vm(int max_xlen, reg_t vm)
 270 {
 271   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 272     return true;
 273   if (max_xlen == 32 && vm == VM_SV32)
 274     return true;
 275   return vm == VM_MBARE;
 276 }
 277
 278 int processor_t::paddr_bits()
 279 {
 280   assert(xlen == max_xlen);
 281   return max_xlen == 64 ? 50 : 34;
 282 }
 283
 284 void processor_t::set_csr(int which, reg_t val)
 285 {
 286   val = zext_xlen(val);
 287   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 288   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 289   switch (which)
 290   {
 291     case CSR_FFLAGS:
 292       dirty_fp_state;
 293       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 294       break;
 295     case CSR_FRM:
 296       dirty_fp_state;
 297       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 298       break;
 299     case CSR_FCSR:
 300       dirty_fp_state;
 301       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 302       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 303       break;
 304     case CSR_MSTATUS: {
 305       if ((val ^ state.mstatus) &
 306           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 307         mmu->flush_tlb();
 308
 309       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 310                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 311                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 312
 313       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 314         mask |= MSTATUS_VM;
 315
 316       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 317
 318       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 319       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 320       if (max_xlen == 32)
 321         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 322       else
 323         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 324
 325       // spike supports the notion of xlen < max_xlen, but current priv spec
 326       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 327       xlen = max_xlen;
 328       break;
 329     }
 330     case CSR_MIP: {
 331       reg_t mask = MIP_SSIP | MIP_STIP;
 332       state.mip = (state.mip & ~mask) | (val & mask);
 333       break;
 334     }
 335     case CSR_MIE:
 336       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 337       break;
 338     case CSR_MIDELEG:
 339       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 340       break;
 341     case CSR_MEDELEG: {
 342       reg_t mask = 0;
 343 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 344 #include "encoding.h"
 345 #undef DECLARE_CAUSE
 346       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 347       break;
 348     }
 349     case CSR_MUCOUNTEREN:
 350       state.mucounteren = val & 7;
 351       break;
 352     case CSR_MSCOUNTEREN:
 353       state.mscounteren = val & 7;
 354       break;
 355     case CSR_SSTATUS: {
 356       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 357                  | SSTATUS_XS | SSTATUS_PUM;
 358       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 359     }
 360     case CSR_SIP:
 361       return set_csr(CSR_MIP,
 362                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 363     case CSR_SIE:
 364       return set_csr(CSR_MIE,
 365                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 366     case CSR_SPTBR: {
 367       // upper bits of sptbr are the ASID; we only support ASID = 0
 368       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 369       break;
 370     }
 371     case CSR_SEPC: state.sepc = val; break;
 372     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 373     case CSR_SSCRATCH: state.sscratch = val; break;
 374     case CSR_SCAUSE: state.scause = val; break;
 375     case CSR_SBADADDR: state.sbadaddr = val; break;
 376     case CSR_MEPC: state.mepc = val; break;
 377     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 378     case CSR_MSCRATCH: state.mscratch = val; break;
 379     case CSR_MCAUSE: state.mcause = val; break;
 380     case CSR_MBADADDR: state.mbadaddr = val; break;
 381     case CSR_DCSR:
 382       state.dcsr.prv = get_field(val, DCSR_PRV);
 383       state.dcsr.step = get_field(val, DCSR_STEP);
 384       // TODO: ndreset and fullreset
 385       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 386       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 387       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 388       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 389       state.dcsr.halt = get_field(val, DCSR_HALT);
 390       break;
 391     case CSR_DPC:
 392       state.dpc = val;
 393       break;
 394     case CSR_DSCRATCH:
 395       state.dscratch = val;
 396       break;
 397   }
 398 }
 399
 400 reg_t processor_t::get_csr(int which)
 401 {
 402   switch (which)
 403   {
 404     case CSR_FFLAGS:
 405       require_fp;
 406       if (!supports_extension('F'))
 407         break;
 408       return state.fflags;
 409     case CSR_FRM:
 410       require_fp;
 411       if (!supports_extension('F'))
 412         break;
 413       return state.frm;
 414     case CSR_FCSR:
 415       require_fp;
 416       if (!supports_extension('F'))
 417         break;
 418       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 419     case CSR_TIME:
 420     case CSR_INSTRET:
 421     case CSR_CYCLE:
 422       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 423         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 424       break;
 425     case CSR_STIME:
 426     case CSR_SINSTRET:
 427     case CSR_SCYCLE:
 428       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 429         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 430       break;
 431     case CSR_MUCOUNTEREN: return state.mucounteren;
 432     case CSR_MSCOUNTEREN: return state.mscounteren;
 433     case CSR_MUCYCLE_DELTA: return 0;
 434     case CSR_MUTIME_DELTA: return 0;
 435     case CSR_MUINSTRET_DELTA: return 0;
 436     case CSR_MSCYCLE_DELTA: return 0;
 437     case CSR_MSTIME_DELTA: return 0;
 438     case CSR_MSINSTRET_DELTA: return 0;
 439     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 440     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 441     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 442     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 443     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 444     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 445     case CSR_MCYCLE: return state.minstret;
 446     case CSR_MINSTRET: return state.minstret;
 447     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 448     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 449     case CSR_SSTATUS: {
 450       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 451                  | SSTATUS_XS | SSTATUS_PUM;
 452       reg_t sstatus = state.mstatus & mask;
 453       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 454           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 455         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 456       return sstatus;
 457     }
 458     case CSR_SIP: return state.mip & state.mideleg;
 459     case CSR_SIE: return state.mie & state.mideleg;
 460     case CSR_SEPC: return state.sepc;
 461     case CSR_SBADADDR: return state.sbadaddr;
 462     case CSR_STVEC: return state.stvec;
 463     case CSR_SCAUSE:
 464       if (max_xlen > xlen)
 465         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 466       return state.scause;
 467     case CSR_SPTBR: return state.sptbr;
 468     case CSR_SSCRATCH: return state.sscratch;
 469     case CSR_MSTATUS: return state.mstatus;
 470     case CSR_MIP: return state.mip;
 471     case CSR_MIE: return state.mie;
 472     case CSR_MEPC: return state.mepc;
 473     case CSR_MSCRATCH: return state.mscratch;
 474     case CSR_MCAUSE: return state.mcause;
 475     case CSR_MBADADDR: return state.mbadaddr;
 476     case CSR_MISA: return isa;
 477     case CSR_MARCHID: return 0;
 478     case CSR_MIMPID: return 0;
 479     case CSR_MVENDORID: return 0;
 480     case CSR_MHARTID: return id;
 481     case CSR_MTVEC: return state.mtvec;
 482     case CSR_MEDELEG: return state.medeleg;
 483     case CSR_MIDELEG: return state.mideleg;
 484     case CSR_TDRSELECT: return 0;
 485     case CSR_DCSR:
 486       {
 487         uint32_t v = 0;
 488         v = set_field(v, DCSR_XDEBUGVER, 1);
 489         v = set_field(v, DCSR_HWBPCOUNT, 0);
 490         v = set_field(v, DCSR_NDRESET, 0);
 491         v = set_field(v, DCSR_FULLRESET, 0);
 492         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 493         v = set_field(v, DCSR_STEP, state.dcsr.step);
 494         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 495         v = set_field(v, DCSR_STOPCYCLE, 0);
 496         v = set_field(v, DCSR_STOPTIME, 0);
 497         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 498         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 499         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 500         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 501         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 502         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 503         return v;
 504       }
 505     case CSR_DPC:
 506       return state.dpc;
 507     case CSR_DSCRATCH:
 508       return state.dscratch;
 509   }
 510   throw trap_illegal_instruction();
 511 }
 512
 513 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 514 {
 515   throw trap_illegal_instruction();
 516 }
 517
 518 insn_func_t processor_t::decode_insn(insn_t insn)
 519 {
 520   // look up opcode in hash table
 521   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 522   insn_desc_t desc = opcode_cache[idx];
 523
 524   if (unlikely(insn.bits() != desc.match)) {
 525     // fall back to linear search
 526     insn_desc_t* p = &instructions[0];
 527     while ((insn.bits() & p->mask) != p->match)
 528       p++;
 529     desc = *p;
 530
 531     if (p->mask != 0 && p > &instructions[0]) {
 532       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 533         // move to front of opcode list to reduce miss penalty
 534         while (--p >= &instructions[0])
 535           *(p+1) = *p;
 536         instructions[0] = desc;
 537       }
 538     }
 539
 540     opcode_cache[idx] = desc;
 541     opcode_cache[idx].match = insn.bits();
 542   }
 543
 544   return xlen == 64 ? desc.rv64 : desc.rv32;
 545 }
 546
 547 void processor_t::register_insn(insn_desc_t desc)
 548 {
 549   instructions.push_back(desc);
 550 }
 551
 552 void processor_t::build_opcode_map()
 553 {
 554   struct cmp {
 555     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 556       if (lhs.match == rhs.match)
 557         return lhs.mask > rhs.mask;
 558       return lhs.match > rhs.match;
 559     }
 560   };
 561   std::sort(instructions.begin(), instructions.end(), cmp());
 562
 563   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 564     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 565 }
 566
 567 void processor_t::register_extension(extension_t* x)
 568 {
 569   for (auto insn : x->get_instructions())
 570     register_insn(insn);
 571   build_opcode_map();
 572   for (auto disasm_insn : x->get_disasms())
 573     disassembler->add_insn(disasm_insn);
 574   if (ext != NULL)
 575     throw std::logic_error("only one extension may be registered");
 576   ext = x;
 577   x->set_processor(this);
 578 }
 579
 580 void processor_t::register_base_instructions()
 581 {
 582   #define DECLARE_INSN(name, match, mask) \
 583     insn_bits_t name##_match = (match), name##_mask = (mask);
 584   #include "encoding.h"
 585   #undef DECLARE_INSN
 586
 587   #define DEFINE_INSN(name) \
 588     REGISTER_INSN(this, name, name##_match, name##_mask)
 589   #include "insn_list.h"
 590   #undef DEFINE_INSN
 591
 592   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 593   build_opcode_map();
 594 }
 595
 596 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 597 {
 598   return false;
 599 }
 600
 601 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 602 {
 603   switch (addr)
 604   {
 605     case 0:
 606       state.mip &= ~MIP_MSIP;
 607       if (bytes[0] & 1)
 608         state.mip |= MIP_MSIP;
 609       return true;
 610
 611     default:
 612       return false;
 613   }
 614 }