riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  24   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  25     id(id), run(false), debug(false), halted(false)
  26 {
  27   parse_isa_string(isa);
  28
  29   mmu = new mmu_t(sim, this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   mtvec = DEFAULT_MTVEC;
 119   load_reservation = -1;
 120 }
 121
 122 void processor_t::set_debug(bool value)
 123 {
 124   debug = value;
 125   if (ext)
 126     ext->set_debug(value);
 127 }
 128
 129 void processor_t::set_halted(bool value)
 130 {
 131   halted = value;
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset(bool value)
 146 {
 147   if (run == !value)
 148     return;
 149   run = !value;
 150
 151   state.reset();
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 void processor_t::raise_interrupt(reg_t which)
 159 {
 160   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 161 }
 162
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt()
 173 {
 174   reg_t pending_interrupts = state.mip & state.mie;
 175
 176   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 177   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 178   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 179
 180   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 181   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 182   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 183
 184   if (enabled_interrupts)
 185     raise_interrupt(ctz(enabled_interrupts));
 186 }
 187
 188 static bool validate_priv(reg_t priv)
 189 {
 190   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 191 }
 192
 193 void processor_t::set_privilege(reg_t prv)
 194 {
 195   assert(validate_priv(prv));
 196   mmu->flush_tlb();
 197   state.prv = prv;
 198 }
 199
 200 void processor_t::take_trap(trap_t& t, reg_t epc)
 201 {
 202   if (debug)
 203     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 204             id, t.name(), epc);
 205
 206   // by default, trap to M-mode, unless delegated to S-mode
 207   reg_t bit = t.cause();
 208   reg_t deleg = state.medeleg;
 209   if (bit & ((reg_t)1 << (max_xlen-1)))
 210     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 211   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 212     // handle the trap in S-mode
 213     state.pc = state.stvec;
 214     state.scause = t.cause();
 215     state.sepc = epc;
 216     if (t.has_badaddr())
 217       state.sbadaddr = t.get_badaddr();
 218
 219     reg_t s = state.mstatus;
 220     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 221     s = set_field(s, MSTATUS_SPP, state.prv);
 222     s = set_field(s, MSTATUS_SIE, 0);
 223     set_csr(CSR_MSTATUS, s);
 224     set_privilege(PRV_S);
 225   } else {
 226     state.pc = state.mtvec;
 227     state.mcause = t.cause();
 228     state.mepc = epc;
 229     if (t.has_badaddr())
 230       state.mbadaddr = t.get_badaddr();
 231
 232     reg_t s = state.mstatus;
 233     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 234     s = set_field(s, MSTATUS_MPP, state.prv);
 235     s = set_field(s, MSTATUS_MIE, 0);
 236     set_csr(CSR_MSTATUS, s);
 237     set_privilege(PRV_M);
 238   }
 239
 240   yield_load_reservation();
 241 }
 242
 243 void processor_t::disasm(insn_t insn)
 244 {
 245   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 246   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 247           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 248 }
 249
 250 static bool validate_vm(int max_xlen, reg_t vm)
 251 {
 252   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 253     return true;
 254   if (max_xlen == 32 && vm == VM_SV32)
 255     return true;
 256   return vm == VM_MBARE;
 257 }
 258
 259 void processor_t::set_csr(int which, reg_t val)
 260 {
 261   val = zext_xlen(val);
 262   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 263   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 264   switch (which)
 265   {
 266     case CSR_FFLAGS:
 267       dirty_fp_state;
 268       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 269       break;
 270     case CSR_FRM:
 271       dirty_fp_state;
 272       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 273       break;
 274     case CSR_FCSR:
 275       dirty_fp_state;
 276       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 277       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 278       break;
 279     case CSR_MSTATUS: {
 280       if ((val ^ state.mstatus) &
 281           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 282         mmu->flush_tlb();
 283
 284       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 285                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 286                  | (ext ? MSTATUS_XS : 0);
 287
 288       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 289         mask |= MSTATUS_VM;
 290       if (validate_priv(get_field(val, MSTATUS_MPP)))
 291         mask |= MSTATUS_MPP;
 292
 293       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 294
 295       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 296       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 297       if (max_xlen == 32)
 298         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 299       else
 300         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 301
 302       // spike supports the notion of xlen < max_xlen, but current priv spec
 303       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 304       xlen = max_xlen;
 305       break;
 306     }
 307     case CSR_MIP: {
 308       reg_t mask = MIP_SSIP | MIP_STIP;
 309       state.mip = (state.mip & ~mask) | (val & mask);
 310       break;
 311     }
 312     case CSR_MIE:
 313       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 314       break;
 315     case CSR_MIDELEG:
 316       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 317       break;
 318     case CSR_MEDELEG: {
 319       reg_t mask = 0;
 320 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 321 #include "encoding.h"
 322 #undef DECLARE_CAUSE
 323       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 324       break;
 325     }
 326     case CSR_MUCOUNTEREN:
 327       state.mucounteren = val & 7;
 328       break;
 329     case CSR_MSCOUNTEREN:
 330       state.mscounteren = val & 7;
 331       break;
 332     case CSR_SSTATUS: {
 333       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 334                  | SSTATUS_XS | SSTATUS_PUM;
 335       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 336     }
 337     case CSR_SIP:
 338       return set_csr(CSR_MIP,
 339                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 340     case CSR_SIE:
 341       return set_csr(CSR_MIE,
 342                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 343     case CSR_SEPC: state.sepc = val; break;
 344     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 345     case CSR_SPTBR: state.sptbr = val; break;
 346     case CSR_SSCRATCH: state.sscratch = val; break;
 347     case CSR_SCAUSE: state.scause = val; break;
 348     case CSR_SBADADDR: state.sbadaddr = val; break;
 349     case CSR_MEPC: state.mepc = val; break;
 350     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 351     case CSR_MSCRATCH: state.mscratch = val; break;
 352     case CSR_MCAUSE: state.mcause = val; break;
 353     case CSR_MBADADDR: state.mbadaddr = val; break;
 354   }
 355 }
 356
 357 reg_t processor_t::get_csr(int which)
 358 {
 359   switch (which)
 360   {
 361     case CSR_FFLAGS:
 362       require_fp;
 363       if (!supports_extension('F'))
 364         break;
 365       return state.fflags;
 366     case CSR_FRM:
 367       require_fp;
 368       if (!supports_extension('F'))
 369         break;
 370       return state.frm;
 371     case CSR_FCSR:
 372       require_fp;
 373       if (!supports_extension('F'))
 374         break;
 375       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 376     case CSR_TIME:
 377     case CSR_INSTRET:
 378     case CSR_CYCLE:
 379       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 380         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 381       break;
 382     case CSR_STIME:
 383     case CSR_SINSTRET:
 384     case CSR_SCYCLE:
 385       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 386         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 387       break;
 388     case CSR_MUCOUNTEREN: return state.mucounteren;
 389     case CSR_MSCOUNTEREN: return state.mscounteren;
 390     case CSR_MUCYCLE_DELTA: return 0;
 391     case CSR_MUTIME_DELTA: return 0;
 392     case CSR_MUINSTRET_DELTA: return 0;
 393     case CSR_MSCYCLE_DELTA: return 0;
 394     case CSR_MSTIME_DELTA: return 0;
 395     case CSR_MSINSTRET_DELTA: return 0;
 396     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 397     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 398     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 399     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 400     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 401     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 402     case CSR_MCYCLE: return state.minstret;
 403     case CSR_MINSTRET: return state.minstret;
 404     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 405     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 406     case CSR_SSTATUS: {
 407       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 408                  | SSTATUS_XS | SSTATUS_PUM;
 409       reg_t sstatus = state.mstatus & mask;
 410       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 411           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 412         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 413       return sstatus;
 414     }
 415     case CSR_SIP: return state.mip & state.mideleg;
 416     case CSR_SIE: return state.mie & state.mideleg;
 417     case CSR_SEPC: return state.sepc;
 418     case CSR_SBADADDR: return state.sbadaddr;
 419     case CSR_STVEC: return state.stvec;
 420     case CSR_SCAUSE:
 421       if (max_xlen > xlen)
 422         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 423       return state.scause;
 424     case CSR_SPTBR: return state.sptbr;
 425     case CSR_SASID: return 0;
 426     case CSR_SSCRATCH: return state.sscratch;
 427     case CSR_MSTATUS: return state.mstatus;
 428     case CSR_MIP: return state.mip;
 429     case CSR_MIE: return state.mie;
 430     case CSR_MEPC: return state.mepc;
 431     case CSR_MSCRATCH: return state.mscratch;
 432     case CSR_MCAUSE: return state.mcause;
 433     case CSR_MBADADDR: return state.mbadaddr;
 434     case CSR_MISA: return isa;
 435     case CSR_MARCHID: return 0;
 436     case CSR_MIMPID: return 0;
 437     case CSR_MVENDORID: return 0;
 438     case CSR_MHARTID: return id;
 439     case CSR_MTVEC: return state.mtvec;
 440     case CSR_MEDELEG: return state.medeleg;
 441     case CSR_MIDELEG: return state.mideleg;
 442   }
 443   throw trap_illegal_instruction();
 444 }
 445
 446 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 447 {
 448   throw trap_illegal_instruction();
 449 }
 450
 451 insn_func_t processor_t::decode_insn(insn_t insn)
 452 {
 453   // look up opcode in hash table
 454   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 455   insn_desc_t desc = opcode_cache[idx];
 456
 457   if (unlikely(insn.bits() != desc.match)) {
 458     // fall back to linear search
 459     insn_desc_t* p = &instructions[0];
 460     while ((insn.bits() & p->mask) != p->match)
 461       p++;
 462     desc = *p;
 463
 464     if (p->mask != 0 && p > &instructions[0]) {
 465       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 466         // move to front of opcode list to reduce miss penalty
 467         while (--p >= &instructions[0])
 468           *(p+1) = *p;
 469         instructions[0] = desc;
 470       }
 471     }
 472
 473     opcode_cache[idx] = desc;
 474     opcode_cache[idx].match = insn.bits();
 475   }
 476
 477   return xlen == 64 ? desc.rv64 : desc.rv32;
 478 }
 479
 480 void processor_t::register_insn(insn_desc_t desc)
 481 {
 482   instructions.push_back(desc);
 483 }
 484
 485 void processor_t::build_opcode_map()
 486 {
 487   struct cmp {
 488     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 489       if (lhs.match == rhs.match)
 490         return lhs.mask > rhs.mask;
 491       return lhs.match > rhs.match;
 492     }
 493   };
 494   std::sort(instructions.begin(), instructions.end(), cmp());
 495
 496   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 497     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 498 }
 499
 500 void processor_t::register_extension(extension_t* x)
 501 {
 502   for (auto insn : x->get_instructions())
 503     register_insn(insn);
 504   build_opcode_map();
 505   for (auto disasm_insn : x->get_disasms())
 506     disassembler->add_insn(disasm_insn);
 507   if (ext != NULL)
 508     throw std::logic_error("only one extension may be registered");
 509   ext = x;
 510   x->set_processor(this);
 511 }
 512
 513 void processor_t::register_base_instructions()
 514 {
 515   #define DECLARE_INSN(name, match, mask) \
 516     insn_bits_t name##_match = (match), name##_mask = (mask);
 517   #include "encoding.h"
 518   #undef DECLARE_INSN
 519
 520   #define DEFINE_INSN(name) \
 521     REGISTER_INSN(this, name, name##_match, name##_mask)
 522   #include "insn_list.h"
 523   #undef DEFINE_INSN
 524
 525   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 526   build_opcode_map();
 527 }
 528
 529 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 530 {
 531   return false;
 532 }
 533
 534 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 535 {
 536   switch (addr)
 537   {
 538     case 0:
 539       state.mip &= ~MIP_MSIP;
 540       if (bytes[0] & 1)
 541         state.mip |= MIP_MSIP;
 542       return true;
 543
 544     default:
 545       return false;
 546   }
 547 }