riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include "gdbserver.h"
  12 #include <cinttypes>
  13 #include <cmath>
  14 #include <cstdlib>
  15 #include <iostream>
  16 #include <assert.h>
  17 #include <limits.h>
  18 #include <stdexcept>
  19 #include <algorithm>
  20
  21 #undef STATE
  22 #define STATE state
  23
  24 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  25   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
  26     id(id), run(false)
  27 {
  28   parse_isa_string(isa);
  29
  30   mmu = new mmu_t(sim, this);
  31
  32   reset(true);
  33
  34   register_base_instructions();
  35 }
  36
  37 processor_t::~processor_t()
  38 {
  39 #ifdef RISCV_ENABLE_HISTOGRAM
  40   if (histogram_enabled)
  41   {
  42     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  43     for (auto it : pc_histogram)
  44       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  45   }
  46 #endif
  47
  48   delete mmu;
  49   delete disassembler;
  50 }
  51
  52 static void bad_isa_string(const char* isa)
  53 {
  54   fprintf(stderr, "error: bad --isa option %s\n", isa);
  55   abort();
  56 }
  57
  58 void processor_t::parse_isa_string(const char* str)
  59 {
  60   std::string lowercase, tmp;
  61   for (const char *r = str; *r; r++)
  62     lowercase += std::tolower(*r);
  63
  64   const char* p = lowercase.c_str();
  65   const char* all_subsets = "imafdc";
  66
  67   max_xlen = 64;
  68   isa = reg_t(2) << 62;
  69
  70   if (strncmp(p, "rv32", 4) == 0)
  71     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  72   else if (strncmp(p, "rv64", 4) == 0)
  73     p += 4;
  74   else if (strncmp(p, "rv", 2) == 0)
  75     p += 2;
  76
  77   if (!*p) {
  78     p = all_subsets;
  79   } else if (*p == 'g') { // treat "G" as "IMAFD"
  80     tmp = std::string("imafd") + (p+1);
  81     p = &tmp[0];
  82   } else if (*p != 'i') {
  83     bad_isa_string(str);
  84   }
  85
  86   isa_string = "rv" + std::to_string(max_xlen) + p;
  87   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121 }
 122
 123 void processor_t::set_debug(bool value)
 124 {
 125   debug = value;
 126   if (ext)
 127     ext->set_debug(value);
 128 }
 129
 130 void processor_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133 #ifndef RISCV_ENABLE_HISTOGRAM
 134   if (value) {
 135     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 136     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 137   }
 138 #endif
 139 }
 140
 141 void processor_t::reset(bool value)
 142 {
 143   if (run == !value)
 144     return;
 145   run = !value;
 146
 147   state.reset();
 148   set_csr(CSR_MSTATUS, state.mstatus);
 149
 150   if (ext)
 151     ext->reset(); // reset the extension
 152 }
 153
 154 void processor_t::raise_interrupt(reg_t which)
 155 {
 156   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 157 }
 158
 159 static int ctz(reg_t val)
 160 {
 161   int res = 0;
 162   if (val)
 163     while ((val & 1) == 0)
 164       val >>= 1, res++;
 165   return res;
 166 }
 167
 168 void processor_t::take_interrupt()
 169 {
 170   reg_t pending_interrupts = state.mip & state.mie;
 171
 172   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 173   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 174   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 175
 176   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 177   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 178   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 179
 180   if (enabled_interrupts)
 181     raise_interrupt(ctz(enabled_interrupts));
 182 }
 183
 184 static bool validate_priv(reg_t priv)
 185 {
 186   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 187 }
 188
 189 void processor_t::set_privilege(reg_t prv)
 190 {
 191   assert(validate_priv(prv));
 192   mmu->flush_tlb();
 193   state.prv = prv;
 194 }
 195
 196 void processor_t::enter_debug_mode(uint8_t cause)
 197 {
 198   fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv);
 199   state.dcsr.cause = cause;
 200   state.dcsr.prv = state.prv;
 201   set_privilege(PRV_M);
 202   state.dpc = state.pc;
 203   state.pc = DEBUG_ROM_START;
 204   debug = true; // TODO
 205 }
 206
 207 void processor_t::take_trap(trap_t& t, reg_t epc)
 208 {
 209   if (debug) {
 210     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 211             id, t.name(), epc);
 212     if (t.has_badaddr())
 213       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 214           t.get_badaddr());
 215   }
 216
 217   if (t.cause() == CAUSE_BREAKPOINT &&
 218           sim->gdbserver && sim->gdbserver->connected()) {
 219     enter_debug_mode(DCSR_CAUSE_SWBP);
 220     return;
 221   }
 222
 223   // by default, trap to M-mode, unless delegated to S-mode
 224   reg_t bit = t.cause();
 225   reg_t deleg = state.medeleg;
 226   if (bit & ((reg_t)1 << (max_xlen-1)))
 227     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 228   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 229     // handle the trap in S-mode
 230     state.pc = state.stvec;
 231     state.scause = t.cause();
 232     state.sepc = epc;
 233     if (t.has_badaddr())
 234       state.sbadaddr = t.get_badaddr();
 235
 236     reg_t s = state.mstatus;
 237     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 238     s = set_field(s, MSTATUS_SPP, state.prv);
 239     s = set_field(s, MSTATUS_SIE, 0);
 240     set_csr(CSR_MSTATUS, s);
 241     set_privilege(PRV_S);
 242   } else {
 243     if (state.dcsr.cause) {
 244       state.pc = DEBUG_ROM_EXCEPTION;
 245     } else {
 246       state.pc = state.mtvec;
 247     }
 248     state.mcause = t.cause();
 249     state.mepc = epc;
 250     if (t.has_badaddr())
 251       state.mbadaddr = t.get_badaddr();
 252
 253     reg_t s = state.mstatus;
 254     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 255     s = set_field(s, MSTATUS_MPP, state.prv);
 256     s = set_field(s, MSTATUS_MIE, 0);
 257     set_csr(CSR_MSTATUS, s);
 258     set_privilege(PRV_M);
 259   }
 260
 261   yield_load_reservation();
 262 }
 263
 264 void processor_t::disasm(insn_t insn)
 265 {
 266   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 267   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 268           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 269 }
 270
 271 static bool validate_vm(int max_xlen, reg_t vm)
 272 {
 273   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 274     return true;
 275   if (max_xlen == 32 && vm == VM_SV32)
 276     return true;
 277   return vm == VM_MBARE;
 278 }
 279
 280 void processor_t::set_csr(int which, reg_t val)
 281 {
 282   fprintf(stderr, "set_csr(0x%x, 0x%lx)\n", which, val);
 283   val = zext_xlen(val);
 284   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 285   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 286   switch (which)
 287   {
 288     case CSR_FFLAGS:
 289       dirty_fp_state;
 290       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 291       break;
 292     case CSR_FRM:
 293       dirty_fp_state;
 294       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 295       break;
 296     case CSR_FCSR:
 297       dirty_fp_state;
 298       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 299       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 300       break;
 301     case CSR_MSTATUS: {
 302       if ((val ^ state.mstatus) &
 303           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 304         mmu->flush_tlb();
 305
 306       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 307                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 308                  | (ext ? MSTATUS_XS : 0);
 309
 310       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 311         mask |= MSTATUS_VM;
 312       if (validate_priv(get_field(val, MSTATUS_MPP)))
 313         mask |= MSTATUS_MPP;
 314
 315       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 316
 317       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 318       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 319       if (max_xlen == 32)
 320         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 321       else
 322         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 323
 324       // spike supports the notion of xlen < max_xlen, but current priv spec
 325       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 326       xlen = max_xlen;
 327       break;
 328     }
 329     case CSR_MIP: {
 330       reg_t mask = MIP_SSIP | MIP_STIP;
 331       state.mip = (state.mip & ~mask) | (val & mask);
 332       break;
 333     }
 334     case CSR_MIE:
 335       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 336       break;
 337     case CSR_MIDELEG:
 338       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 339       break;
 340     case CSR_MEDELEG: {
 341       reg_t mask = 0;
 342 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 343 #include "encoding.h"
 344 #undef DECLARE_CAUSE
 345       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 346       break;
 347     }
 348     case CSR_MUCOUNTEREN:
 349       state.mucounteren = val & 7;
 350       break;
 351     case CSR_MSCOUNTEREN:
 352       state.mscounteren = val & 7;
 353       break;
 354     case CSR_SSTATUS: {
 355       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 356                  | SSTATUS_XS | SSTATUS_PUM;
 357       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 358     }
 359     case CSR_SIP:
 360       return set_csr(CSR_MIP,
 361                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 362     case CSR_SIE:
 363       return set_csr(CSR_MIE,
 364                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 365     case CSR_SEPC: state.sepc = val; break;
 366     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 367     case CSR_SPTBR: state.sptbr = val; break;
 368     case CSR_SSCRATCH: state.sscratch = val; break;
 369     case CSR_SCAUSE: state.scause = val; break;
 370     case CSR_SBADADDR: state.sbadaddr = val; break;
 371     case CSR_MEPC: state.mepc = val; break;
 372     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 373     case CSR_MSCRATCH: state.mscratch = val; break;
 374     case CSR_MCAUSE: state.mcause = val; break;
 375     case CSR_MBADADDR: state.mbadaddr = val; break;
 376     case DCSR_ADDRESS:
 377       // TODO: Use get_field style
 378       state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
 379       state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
 380       // TODO: ndreset and fullreset
 381       state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
 382       state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
 383       state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
 384       state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
 385       state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
 386       break;
 387     case DPC_ADDRESS:
 388       state.dpc = val;
 389       break;
 390     case DSCRATCH_ADDRESS:
 391       state.dscratch = val;
 392       break;
 393   }
 394 }
 395
 396 reg_t processor_t::get_csr(int which)
 397 {
 398   switch (which)
 399   {
 400     case CSR_FFLAGS:
 401       require_fp;
 402       if (!supports_extension('F'))
 403         break;
 404       return state.fflags;
 405     case CSR_FRM:
 406       require_fp;
 407       if (!supports_extension('F'))
 408         break;
 409       return state.frm;
 410     case CSR_FCSR:
 411       require_fp;
 412       if (!supports_extension('F'))
 413         break;
 414       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 415     case CSR_TIME:
 416     case CSR_INSTRET:
 417     case CSR_CYCLE:
 418       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 419         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 420       break;
 421     case CSR_STIME:
 422     case CSR_SINSTRET:
 423     case CSR_SCYCLE:
 424       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 425         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 426       break;
 427     case CSR_MUCOUNTEREN: return state.mucounteren;
 428     case CSR_MSCOUNTEREN: return state.mscounteren;
 429     case CSR_MUCYCLE_DELTA: return 0;
 430     case CSR_MUTIME_DELTA: return 0;
 431     case CSR_MUINSTRET_DELTA: return 0;
 432     case CSR_MSCYCLE_DELTA: return 0;
 433     case CSR_MSTIME_DELTA: return 0;
 434     case CSR_MSINSTRET_DELTA: return 0;
 435     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 436     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 437     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 438     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 439     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 440     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 441     case CSR_MCYCLE: return state.minstret;
 442     case CSR_MINSTRET: return state.minstret;
 443     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 444     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 445     case CSR_SSTATUS: {
 446       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 447                  | SSTATUS_XS | SSTATUS_PUM;
 448       reg_t sstatus = state.mstatus & mask;
 449       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 450           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 451         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 452       return sstatus;
 453     }
 454     case CSR_SIP: return state.mip & state.mideleg;
 455     case CSR_SIE: return state.mie & state.mideleg;
 456     case CSR_SEPC: return state.sepc;
 457     case CSR_SBADADDR: return state.sbadaddr;
 458     case CSR_STVEC: return state.stvec;
 459     case CSR_SCAUSE:
 460       if (max_xlen > xlen)
 461         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 462       return state.scause;
 463     case CSR_SPTBR: return state.sptbr;
 464     case CSR_SASID: return 0;
 465     case CSR_SSCRATCH: return state.sscratch;
 466     case CSR_MSTATUS: return state.mstatus;
 467     case CSR_MIP: return state.mip;
 468     case CSR_MIE: return state.mie;
 469     case CSR_MEPC: return state.mepc;
 470     case CSR_MSCRATCH: return state.mscratch;
 471     case CSR_MCAUSE: return state.mcause;
 472     case CSR_MBADADDR: return state.mbadaddr;
 473     case CSR_MISA: return isa;
 474     case CSR_MARCHID: return 0;
 475     case CSR_MIMPID: return 0;
 476     case CSR_MVENDORID: return 0;
 477     case CSR_MHARTID: return id;
 478     case CSR_MTVEC: return state.mtvec;
 479     case CSR_MEDELEG: return state.medeleg;
 480     case CSR_MIDELEG: return state.mideleg;
 481     case DCSR_ADDRESS:
 482       {
 483         uint32_t value =
 484           (1 << DCSR_XDEBUGVER_OFFSET) |
 485           (0 << DCSR_HWBPCOUNT_OFFSET) |
 486           (0 << DCSR_NDRESET_OFFSET) |
 487           (0 << DCSR_FULLRESET_OFFSET) |
 488           (state.dcsr.prv << DCSR_PRV_OFFSET) |
 489           (state.dcsr.step << DCSR_STEP_OFFSET) |
 490           (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
 491           (0 << DCSR_STOPCYCLE_OFFSET) |
 492           (0 << DCSR_STOPTIME_OFFSET) |
 493           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
 494           (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
 495           (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
 496           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
 497           (state.dcsr.halt << DCSR_HALT_OFFSET) |
 498           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
 499         return value;
 500       }
 501     case DPC_ADDRESS:
 502       return state.dpc;
 503     case DSCRATCH_ADDRESS:
 504       return state.dscratch;
 505   }
 506   throw trap_illegal_instruction();
 507 }
 508
 509 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 510 {
 511   throw trap_illegal_instruction();
 512 }
 513
 514 insn_func_t processor_t::decode_insn(insn_t insn)
 515 {
 516   // look up opcode in hash table
 517   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 518   insn_desc_t desc = opcode_cache[idx];
 519
 520   if (unlikely(insn.bits() != desc.match)) {
 521     // fall back to linear search
 522     insn_desc_t* p = &instructions[0];
 523     while ((insn.bits() & p->mask) != p->match)
 524       p++;
 525     desc = *p;
 526
 527     if (p->mask != 0 && p > &instructions[0]) {
 528       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 529         // move to front of opcode list to reduce miss penalty
 530         while (--p >= &instructions[0])
 531           *(p+1) = *p;
 532         instructions[0] = desc;
 533       }
 534     }
 535
 536     opcode_cache[idx] = desc;
 537     opcode_cache[idx].match = insn.bits();
 538   }
 539
 540   return xlen == 64 ? desc.rv64 : desc.rv32;
 541 }
 542
 543 void processor_t::register_insn(insn_desc_t desc)
 544 {
 545   instructions.push_back(desc);
 546 }
 547
 548 void processor_t::build_opcode_map()
 549 {
 550   struct cmp {
 551     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 552       if (lhs.match == rhs.match)
 553         return lhs.mask > rhs.mask;
 554       return lhs.match > rhs.match;
 555     }
 556   };
 557   std::sort(instructions.begin(), instructions.end(), cmp());
 558
 559   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 560     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 561 }
 562
 563 void processor_t::register_extension(extension_t* x)
 564 {
 565   for (auto insn : x->get_instructions())
 566     register_insn(insn);
 567   build_opcode_map();
 568   for (auto disasm_insn : x->get_disasms())
 569     disassembler->add_insn(disasm_insn);
 570   if (ext != NULL)
 571     throw std::logic_error("only one extension may be registered");
 572   ext = x;
 573   x->set_processor(this);
 574 }
 575
 576 void processor_t::register_base_instructions()
 577 {
 578   #define DECLARE_INSN(name, match, mask) \
 579     insn_bits_t name##_match = (match), name##_mask = (mask);
 580   #include "encoding.h"
 581   #undef DECLARE_INSN
 582
 583   #define DEFINE_INSN(name) \
 584     REGISTER_INSN(this, name, name##_match, name##_mask)
 585   #include "insn_list.h"
 586   #undef DEFINE_INSN
 587
 588   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 589   build_opcode_map();
 590 }
 591
 592 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 593 {
 594   return false;
 595 }
 596
 597 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 598 {
 599   switch (addr)
 600   {
 601     case 0:
 602       state.mip &= ~MIP_MSIP;
 603       if (bytes[0] & 1)
 604         state.mip |= MIP_MSIP;
 605       return true;
 606
 607     default:
 608       return false;
 609   }
 610 }