riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include "gdbserver.h"
  12 #include <cinttypes>
  13 #include <cmath>
  14 #include <cstdlib>
  15 #include <iostream>
  16 #include <assert.h>
  17 #include <limits.h>
  18 #include <stdexcept>
  19 #include <algorithm>
  20
  21 #undef STATE
  22 #define STATE state
  23
  24 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  25   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
  26     id(id), run(false)
  27 {
  28   parse_isa_string(isa);
  29
  30   mmu = new mmu_t(sim, this);
  31
  32   reset(true);
  33
  34   register_base_instructions();
  35 }
  36
  37 processor_t::~processor_t()
  38 {
  39 #ifdef RISCV_ENABLE_HISTOGRAM
  40   if (histogram_enabled)
  41   {
  42     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  43     for (auto it : pc_histogram)
  44       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  45   }
  46 #endif
  47
  48   delete mmu;
  49   delete disassembler;
  50 }
  51
  52 static void bad_isa_string(const char* isa)
  53 {
  54   fprintf(stderr, "error: bad --isa option %s\n", isa);
  55   abort();
  56 }
  57
  58 void processor_t::parse_isa_string(const char* str)
  59 {
  60   std::string lowercase, tmp;
  61   for (const char *r = str; *r; r++)
  62     lowercase += std::tolower(*r);
  63
  64   const char* p = lowercase.c_str();
  65   const char* all_subsets = "imafdc";
  66
  67   max_xlen = 64;
  68   isa = reg_t(2) << 62;
  69
  70   if (strncmp(p, "rv32", 4) == 0)
  71     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  72   else if (strncmp(p, "rv64", 4) == 0)
  73     p += 4;
  74   else if (strncmp(p, "rv", 2) == 0)
  75     p += 2;
  76
  77   if (!*p) {
  78     p = all_subsets;
  79   } else if (*p == 'g') { // treat "G" as "IMAFD"
  80     tmp = std::string("imafd") + (p+1);
  81     p = &tmp[0];
  82   } else if (*p != 'i') {
  83     bad_isa_string(str);
  84   }
  85
  86   isa_string = "rv" + std::to_string(max_xlen) + p;
  87   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121 }
 122
 123 void processor_t::set_debug(bool value)
 124 {
 125   debug = value;
 126   if (ext)
 127     ext->set_debug(value);
 128 }
 129
 130 void processor_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133 #ifndef RISCV_ENABLE_HISTOGRAM
 134   if (value) {
 135     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 136     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 137   }
 138 #endif
 139 }
 140
 141 void processor_t::reset(bool value)
 142 {
 143   if (run == !value)
 144     return;
 145   run = !value;
 146
 147   state.reset();
 148   set_csr(CSR_MSTATUS, state.mstatus);
 149
 150   if (ext)
 151     ext->reset(); // reset the extension
 152 }
 153
 154 void processor_t::raise_interrupt(reg_t which)
 155 {
 156   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 157 }
 158
 159 static int ctz(reg_t val)
 160 {
 161   int res = 0;
 162   if (val)
 163     while ((val & 1) == 0)
 164       val >>= 1, res++;
 165   return res;
 166 }
 167
 168 void processor_t::take_interrupt()
 169 {
 170   reg_t pending_interrupts = state.mip & state.mie;
 171
 172   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 173   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 174   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 175
 176   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 177   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 178   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 179
 180   if (enabled_interrupts)
 181     raise_interrupt(ctz(enabled_interrupts));
 182 }
 183
 184 static bool validate_priv(reg_t priv)
 185 {
 186   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 187 }
 188
 189 void processor_t::set_privilege(reg_t prv)
 190 {
 191   assert(validate_priv(prv));
 192   mmu->flush_tlb();
 193   state.prv = prv;
 194 }
 195
 196 void processor_t::enter_debug_mode(uint8_t cause)
 197 {
 198   fprintf(stderr, "enter_debug_mode(%d)\n", cause);
 199   state.dcsr.cause = cause;
 200   state.dcsr.prv = state.prv;
 201   state.prv = PRV_M;
 202   state.dpc = state.pc;
 203   state.pc = DEBUG_ROM_START;
 204   debug = true; // TODO
 205 }
 206
 207 void processor_t::take_trap(trap_t& t, reg_t epc)
 208 {
 209   if (debug)
 210     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 211             id, t.name(), epc);
 212
 213   if (t.cause() == CAUSE_BREAKPOINT &&
 214           sim->gdbserver && sim->gdbserver->connected()) {
 215     enter_debug_mode(DCSR_CAUSE_SWBP);
 216     return;
 217   }
 218
 219   // by default, trap to M-mode, unless delegated to S-mode
 220   reg_t bit = t.cause();
 221   reg_t deleg = state.medeleg;
 222   if (bit & ((reg_t)1 << (max_xlen-1)))
 223     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 224   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 225     // handle the trap in S-mode
 226     state.pc = state.stvec;
 227     state.scause = t.cause();
 228     state.sepc = epc;
 229     if (t.has_badaddr())
 230       state.sbadaddr = t.get_badaddr();
 231
 232     reg_t s = state.mstatus;
 233     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 234     s = set_field(s, MSTATUS_SPP, state.prv);
 235     s = set_field(s, MSTATUS_SIE, 0);
 236     set_csr(CSR_MSTATUS, s);
 237     set_privilege(PRV_S);
 238   } else {
 239     if (state.dcsr.cause) {
 240       state.pc = DEBUG_ROM_EXCEPTION;
 241     } else {
 242       state.pc = state.mtvec;
 243     }
 244     state.mcause = t.cause();
 245     state.mepc = epc;
 246     if (t.has_badaddr())
 247       state.mbadaddr = t.get_badaddr();
 248
 249     reg_t s = state.mstatus;
 250     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 251     s = set_field(s, MSTATUS_MPP, state.prv);
 252     s = set_field(s, MSTATUS_MIE, 0);
 253     set_csr(CSR_MSTATUS, s);
 254     set_privilege(PRV_M);
 255   }
 256
 257   yield_load_reservation();
 258 }
 259
 260 void processor_t::disasm(insn_t insn)
 261 {
 262   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 263   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 264           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 265 }
 266
 267 static bool validate_vm(int max_xlen, reg_t vm)
 268 {
 269   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 270     return true;
 271   if (max_xlen == 32 && vm == VM_SV32)
 272     return true;
 273   return vm == VM_MBARE;
 274 }
 275
 276 void processor_t::set_csr(int which, reg_t val)
 277 {
 278   val = zext_xlen(val);
 279   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 280   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 281   switch (which)
 282   {
 283     case CSR_FFLAGS:
 284       dirty_fp_state;
 285       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 286       break;
 287     case CSR_FRM:
 288       dirty_fp_state;
 289       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 290       break;
 291     case CSR_FCSR:
 292       dirty_fp_state;
 293       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 294       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 295       break;
 296     case CSR_MSTATUS: {
 297       if ((val ^ state.mstatus) &
 298           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 299         mmu->flush_tlb();
 300
 301       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 302                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 303                  | (ext ? MSTATUS_XS : 0);
 304
 305       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 306         mask |= MSTATUS_VM;
 307       if (validate_priv(get_field(val, MSTATUS_MPP)))
 308         mask |= MSTATUS_MPP;
 309
 310       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 311
 312       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 313       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 314       if (max_xlen == 32)
 315         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 316       else
 317         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 318
 319       // spike supports the notion of xlen < max_xlen, but current priv spec
 320       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 321       xlen = max_xlen;
 322       break;
 323     }
 324     case CSR_MIP: {
 325       reg_t mask = MIP_SSIP | MIP_STIP;
 326       state.mip = (state.mip & ~mask) | (val & mask);
 327       break;
 328     }
 329     case CSR_MIE:
 330       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 331       break;
 332     case CSR_MIDELEG:
 333       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 334       break;
 335     case CSR_MEDELEG: {
 336       reg_t mask = 0;
 337 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 338 #include "encoding.h"
 339 #undef DECLARE_CAUSE
 340       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 341       break;
 342     }
 343     case CSR_MUCOUNTEREN:
 344       state.mucounteren = val & 7;
 345       break;
 346     case CSR_MSCOUNTEREN:
 347       state.mscounteren = val & 7;
 348       break;
 349     case CSR_SSTATUS: {
 350       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 351                  | SSTATUS_XS | SSTATUS_PUM;
 352       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 353     }
 354     case CSR_SIP:
 355       return set_csr(CSR_MIP,
 356                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 357     case CSR_SIE:
 358       return set_csr(CSR_MIE,
 359                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 360     case CSR_SEPC: state.sepc = val; break;
 361     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 362     case CSR_SPTBR: state.sptbr = val; break;
 363     case CSR_SSCRATCH: state.sscratch = val; break;
 364     case CSR_SCAUSE: state.scause = val; break;
 365     case CSR_SBADADDR: state.sbadaddr = val; break;
 366     case CSR_MEPC: state.mepc = val; break;
 367     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 368     case CSR_MSCRATCH: state.mscratch = val; break;
 369     case CSR_MCAUSE: state.mcause = val; break;
 370     case CSR_MBADADDR: state.mbadaddr = val; break;
 371     case DCSR_ADDRESS:
 372       // TODO: Use get_field style
 373       state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
 374       state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
 375       // TODO: ndreset and fullreset
 376       state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
 377       state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
 378       state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
 379       state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
 380       state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
 381       break;
 382     case DPC_ADDRESS:
 383       state.dpc = val;
 384       break;
 385     case DSCRATCH_ADDRESS:
 386       state.dscratch = val;
 387       break;
 388   }
 389 }
 390
 391 reg_t processor_t::get_csr(int which)
 392 {
 393   switch (which)
 394   {
 395     case CSR_FFLAGS:
 396       require_fp;
 397       if (!supports_extension('F'))
 398         break;
 399       return state.fflags;
 400     case CSR_FRM:
 401       require_fp;
 402       if (!supports_extension('F'))
 403         break;
 404       return state.frm;
 405     case CSR_FCSR:
 406       require_fp;
 407       if (!supports_extension('F'))
 408         break;
 409       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 410     case CSR_TIME:
 411     case CSR_INSTRET:
 412     case CSR_CYCLE:
 413       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 414         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 415       break;
 416     case CSR_STIME:
 417     case CSR_SINSTRET:
 418     case CSR_SCYCLE:
 419       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 420         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 421       break;
 422     case CSR_MUCOUNTEREN: return state.mucounteren;
 423     case CSR_MSCOUNTEREN: return state.mscounteren;
 424     case CSR_MUCYCLE_DELTA: return 0;
 425     case CSR_MUTIME_DELTA: return 0;
 426     case CSR_MUINSTRET_DELTA: return 0;
 427     case CSR_MSCYCLE_DELTA: return 0;
 428     case CSR_MSTIME_DELTA: return 0;
 429     case CSR_MSINSTRET_DELTA: return 0;
 430     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 431     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 432     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 433     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 434     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 435     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 436     case CSR_MCYCLE: return state.minstret;
 437     case CSR_MINSTRET: return state.minstret;
 438     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 439     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 440     case CSR_SSTATUS: {
 441       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 442                  | SSTATUS_XS | SSTATUS_PUM;
 443       reg_t sstatus = state.mstatus & mask;
 444       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 445           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 446         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 447       return sstatus;
 448     }
 449     case CSR_SIP: return state.mip & state.mideleg;
 450     case CSR_SIE: return state.mie & state.mideleg;
 451     case CSR_SEPC: return state.sepc;
 452     case CSR_SBADADDR: return state.sbadaddr;
 453     case CSR_STVEC: return state.stvec;
 454     case CSR_SCAUSE:
 455       if (max_xlen > xlen)
 456         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 457       return state.scause;
 458     case CSR_SPTBR: return state.sptbr;
 459     case CSR_SASID: return 0;
 460     case CSR_SSCRATCH: return state.sscratch;
 461     case CSR_MSTATUS: return state.mstatus;
 462     case CSR_MIP: return state.mip;
 463     case CSR_MIE: return state.mie;
 464     case CSR_MEPC: return state.mepc;
 465     case CSR_MSCRATCH: return state.mscratch;
 466     case CSR_MCAUSE: return state.mcause;
 467     case CSR_MBADADDR: return state.mbadaddr;
 468     case CSR_MISA: return isa;
 469     case CSR_MARCHID: return 0;
 470     case CSR_MIMPID: return 0;
 471     case CSR_MVENDORID: return 0;
 472     case CSR_MHARTID: return id;
 473     case CSR_MTVEC: return state.mtvec;
 474     case CSR_MEDELEG: return state.medeleg;
 475     case CSR_MIDELEG: return state.mideleg;
 476     case DCSR_ADDRESS:
 477       {
 478         uint32_t value =
 479           (1 << DCSR_XDEBUGVER_OFFSET) |
 480           (0 << DCSR_HWBPCOUNT_OFFSET) |
 481           (0 << DCSR_NDRESET_OFFSET) |
 482           (0 << DCSR_FULLRESET_OFFSET) |
 483           (state.dcsr.prv << DCSR_PRV_OFFSET) |
 484           (state.dcsr.step << DCSR_STEP_OFFSET) |
 485           (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
 486           (0 << DCSR_STOPCYCLE_OFFSET) |
 487           (0 << DCSR_STOPTIME_OFFSET) |
 488           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
 489           (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
 490           (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
 491           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
 492           (state.dcsr.halt << DCSR_HALT_OFFSET) |
 493           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
 494         return value;
 495       }
 496     case DPC_ADDRESS:
 497       return state.dpc;
 498     case DSCRATCH_ADDRESS:
 499       return state.dscratch;
 500   }
 501   throw trap_illegal_instruction();
 502 }
 503
 504 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 505 {
 506   throw trap_illegal_instruction();
 507 }
 508
 509 insn_func_t processor_t::decode_insn(insn_t insn)
 510 {
 511   // look up opcode in hash table
 512   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 513   insn_desc_t desc = opcode_cache[idx];
 514
 515   if (unlikely(insn.bits() != desc.match)) {
 516     // fall back to linear search
 517     insn_desc_t* p = &instructions[0];
 518     while ((insn.bits() & p->mask) != p->match)
 519       p++;
 520     desc = *p;
 521
 522     if (p->mask != 0 && p > &instructions[0]) {
 523       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 524         // move to front of opcode list to reduce miss penalty
 525         while (--p >= &instructions[0])
 526           *(p+1) = *p;
 527         instructions[0] = desc;
 528       }
 529     }
 530
 531     opcode_cache[idx] = desc;
 532     opcode_cache[idx].match = insn.bits();
 533   }
 534
 535   return xlen == 64 ? desc.rv64 : desc.rv32;
 536 }
 537
 538 void processor_t::register_insn(insn_desc_t desc)
 539 {
 540   instructions.push_back(desc);
 541 }
 542
 543 void processor_t::build_opcode_map()
 544 {
 545   struct cmp {
 546     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 547       if (lhs.match == rhs.match)
 548         return lhs.mask > rhs.mask;
 549       return lhs.match > rhs.match;
 550     }
 551   };
 552   std::sort(instructions.begin(), instructions.end(), cmp());
 553
 554   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 555     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 556 }
 557
 558 void processor_t::register_extension(extension_t* x)
 559 {
 560   for (auto insn : x->get_instructions())
 561     register_insn(insn);
 562   build_opcode_map();
 563   for (auto disasm_insn : x->get_disasms())
 564     disassembler->add_insn(disasm_insn);
 565   if (ext != NULL)
 566     throw std::logic_error("only one extension may be registered");
 567   ext = x;
 568   x->set_processor(this);
 569 }
 570
 571 void processor_t::register_base_instructions()
 572 {
 573   #define DECLARE_INSN(name, match, mask) \
 574     insn_bits_t name##_match = (match), name##_mask = (mask);
 575   #include "encoding.h"
 576   #undef DECLARE_INSN
 577
 578   #define DEFINE_INSN(name) \
 579     REGISTER_INSN(this, name, name##_match, name##_mask)
 580   #include "insn_list.h"
 581   #undef DEFINE_INSN
 582
 583   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 584   build_opcode_map();
 585 }
 586
 587 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 588 {
 589   return false;
 590 }
 591
 592 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 593 {
 594   switch (addr)
 595   {
 596     case 0:
 597       state.mip &= ~MIP_MSIP;
 598       if (bytes[0] & 1)
 599         state.mip |= MIP_MSIP;
 600       return true;
 601
 602     default:
 603       return false;
 604   }
 605 }