riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   state.dcsr.cause = cause;
 193   state.dcsr.prv = state.prv;
 194   set_privilege(PRV_M);
 195   state.dpc = state.pc;
 196   state.pc = debug_rom_entry();
 197 }
 198
 199 void processor_t::take_trap(trap_t& t, reg_t epc)
 200 {
 201   if (debug) {
 202     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 203             id, t.name(), epc);
 204     if (t.has_badaddr())
 205       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 206           t.get_badaddr());
 207   }
 208
 209   if (state.dcsr.cause) {
 210     if (t.cause() == CAUSE_BREAKPOINT) {
 211       state.pc = debug_rom_entry();
 212     } else {
 213       state.pc = DEBUG_ROM_EXCEPTION;
 214     }
 215     return;
 216   }
 217
 218   if (t.cause() == CAUSE_BREAKPOINT && (
 219               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 220               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 221               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 222               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 223     enter_debug_mode(DCSR_CAUSE_SWBP);
 224     return;
 225   }
 226
 227   // by default, trap to M-mode, unless delegated to S-mode
 228   reg_t bit = t.cause();
 229   reg_t deleg = state.medeleg;
 230   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 231   if (interrupt)
 232     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 233   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 234     // handle the trap in S-mode
 235     state.pc = state.stvec;
 236     state.scause = t.cause();
 237     state.sepc = epc;
 238     if (t.has_badaddr())
 239       state.sbadaddr = t.get_badaddr();
 240
 241     reg_t s = state.mstatus;
 242     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 243     s = set_field(s, MSTATUS_SPP, state.prv);
 244     s = set_field(s, MSTATUS_SIE, 0);
 245     set_csr(CSR_MSTATUS, s);
 246     set_privilege(PRV_S);
 247   } else {
 248     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 249     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 250     state.mepc = epc;
 251     state.mcause = t.cause();
 252     if (t.has_badaddr())
 253       state.mbadaddr = t.get_badaddr();
 254
 255     reg_t s = state.mstatus;
 256     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 257     s = set_field(s, MSTATUS_MPP, state.prv);
 258     s = set_field(s, MSTATUS_MIE, 0);
 259     set_csr(CSR_MSTATUS, s);
 260     set_privilege(PRV_M);
 261   }
 262
 263   yield_load_reservation();
 264 }
 265
 266 void processor_t::disasm(insn_t insn)
 267 {
 268   static uint64_t last_pc = 1, last_bits;
 269   static uint64_t executions = 1;
 270
 271   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 272   if (last_pc != state.pc || last_bits != bits) {
 273     if (executions != 1) {
 274       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 275     }
 276
 277     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 278             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 279     last_pc = state.pc;
 280     last_bits = bits;
 281     executions = 1;
 282   } else {
 283     executions++;
 284   }
 285 }
 286
 287 int processor_t::paddr_bits()
 288 {
 289   assert(xlen == max_xlen);
 290   return max_xlen == 64 ? 50 : 34;
 291 }
 292
 293 void processor_t::set_csr(int which, reg_t val)
 294 {
 295   val = zext_xlen(val);
 296   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 297   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 298   switch (which)
 299   {
 300     case CSR_FFLAGS:
 301       dirty_fp_state;
 302       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 303       break;
 304     case CSR_FRM:
 305       dirty_fp_state;
 306       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 307       break;
 308     case CSR_FCSR:
 309       dirty_fp_state;
 310       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 311       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 312       break;
 313     case CSR_MSTATUS: {
 314       if ((val ^ state.mstatus) &
 315           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 316         mmu->flush_tlb();
 317
 318       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 319                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 320                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 321                  | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
 322
 323       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 324
 325       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 326       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 327       if (max_xlen == 32)
 328         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 329       else
 330         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 331
 332       // spike supports the notion of xlen < max_xlen, but current priv spec
 333       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 334       xlen = max_xlen;
 335       break;
 336     }
 337     case CSR_MIP: {
 338       reg_t mask = MIP_SSIP | MIP_STIP;
 339       state.mip = (state.mip & ~mask) | (val & mask);
 340       break;
 341     }
 342     case CSR_MIE:
 343       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 344       break;
 345     case CSR_MIDELEG:
 346       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 347       break;
 348     case CSR_MEDELEG: {
 349       reg_t mask = 0;
 350 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 351 #include "encoding.h"
 352 #undef DECLARE_CAUSE
 353       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 354       break;
 355     }
 356     case CSR_MINSTRET:
 357     case CSR_MCYCLE:
 358       if (xlen == 32)
 359         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 360       else
 361         state.minstret = val;
 362       break;
 363     case CSR_MINSTRETH:
 364     case CSR_MCYCLEH:
 365       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 366       break;
 367     case CSR_SCOUNTEREN:
 368       state.scounteren = val;
 369       break;
 370     case CSR_MCOUNTEREN:
 371       state.mcounteren = val;
 372       break;
 373     case CSR_SSTATUS: {
 374       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 375                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 376       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 377     }
 378     case CSR_SIP: {
 379       reg_t mask = MIP_SSIP & state.mideleg;
 380       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 381     }
 382     case CSR_SIE:
 383       return set_csr(CSR_MIE,
 384                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 385     case CSR_SPTBR: {
 386       mmu->flush_tlb();
 387       if (max_xlen == 32)
 388         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 389       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 390                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 391                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 392         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 393       break;
 394     }
 395     case CSR_SEPC: state.sepc = val; break;
 396     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 397     case CSR_SSCRATCH: state.sscratch = val; break;
 398     case CSR_SCAUSE: state.scause = val; break;
 399     case CSR_SBADADDR: state.sbadaddr = val; break;
 400     case CSR_MEPC: state.mepc = val; break;
 401     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 402     case CSR_MSCRATCH: state.mscratch = val; break;
 403     case CSR_MCAUSE: state.mcause = val; break;
 404     case CSR_MBADADDR: state.mbadaddr = val; break;
 405     case CSR_MISA: {
 406       if (!(val & (1L << ('F' - 'A'))))
 407         val &= ~(1L << ('D' - 'A'));
 408
 409       // allow MAFDC bits in MISA to be modified
 410       reg_t mask = 0;
 411       mask |= 1L << ('M' - 'A');
 412       mask |= 1L << ('A' - 'A');
 413       mask |= 1L << ('F' - 'A');
 414       mask |= 1L << ('D' - 'A');
 415       mask |= 1L << ('C' - 'A');
 416       mask &= max_isa;
 417
 418       isa = (val & mask) | (isa & ~mask);
 419       break;
 420     }
 421     case CSR_TSELECT:
 422       if (val < state.num_triggers) {
 423         state.tselect = val;
 424       }
 425       break;
 426     case CSR_TDATA1:
 427       {
 428         mcontrol_t *mc = &state.mcontrol[state.tselect];
 429         if (mc->dmode && !state.dcsr.cause) {
 430           break;
 431         }
 432         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 433         mc->select = get_field(val, MCONTROL_SELECT);
 434         mc->timing = get_field(val, MCONTROL_TIMING);
 435         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 436         mc->chain = get_field(val, MCONTROL_CHAIN);
 437         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 438         mc->m = get_field(val, MCONTROL_M);
 439         mc->h = get_field(val, MCONTROL_H);
 440         mc->s = get_field(val, MCONTROL_S);
 441         mc->u = get_field(val, MCONTROL_U);
 442         mc->execute = get_field(val, MCONTROL_EXECUTE);
 443         mc->store = get_field(val, MCONTROL_STORE);
 444         mc->load = get_field(val, MCONTROL_LOAD);
 445         // Assume we're here because of csrw.
 446         if (mc->execute)
 447           mc->timing = 0;
 448         trigger_updated();
 449       }
 450       break;
 451     case CSR_TDATA2:
 452       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 453         break;
 454       }
 455       if (state.tselect < state.num_triggers) {
 456         state.tdata2[state.tselect] = val;
 457       }
 458       break;
 459     case CSR_DCSR:
 460       state.dcsr.prv = get_field(val, DCSR_PRV);
 461       state.dcsr.step = get_field(val, DCSR_STEP);
 462       // TODO: ndreset and fullreset
 463       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 464       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 465       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 466       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 467       state.dcsr.halt = get_field(val, DCSR_HALT);
 468       break;
 469     case CSR_DPC:
 470       state.dpc = val;
 471       break;
 472     case CSR_DSCRATCH:
 473       state.dscratch = val;
 474       break;
 475   }
 476 }
 477
 478 reg_t processor_t::get_csr(int which)
 479 {
 480   uint32_t ctr_en = -1;
 481   if (state.prv < PRV_M)
 482     ctr_en &= state.mcounteren;
 483   if (state.prv < PRV_S)
 484     ctr_en &= state.scounteren;
 485   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 486
 487   if (ctr_ok) {
 488     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 489       return 0;
 490     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 491       return 0;
 492   }
 493   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 494     return 0;
 495   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 496     return 0;
 497   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 498     return 0;
 499
 500   switch (which)
 501   {
 502     case CSR_FFLAGS:
 503       require_fp;
 504       if (!supports_extension('F'))
 505         break;
 506       return state.fflags;
 507     case CSR_FRM:
 508       require_fp;
 509       if (!supports_extension('F'))
 510         break;
 511       return state.frm;
 512     case CSR_FCSR:
 513       require_fp;
 514       if (!supports_extension('F'))
 515         break;
 516       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 517     case CSR_INSTRET:
 518     case CSR_CYCLE:
 519       if (ctr_ok)
 520         return state.minstret;
 521       break;
 522     case CSR_MINSTRET:
 523     case CSR_MCYCLE:
 524       return state.minstret;
 525     case CSR_MINSTRETH:
 526     case CSR_MCYCLEH:
 527       if (xlen == 32)
 528         return state.minstret >> 32;
 529       break;
 530     case CSR_SCOUNTEREN: return state.scounteren;
 531     case CSR_MCOUNTEREN: return state.mcounteren;
 532     case CSR_SSTATUS: {
 533       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 534                  | SSTATUS_XS | SSTATUS_SUM;
 535       reg_t sstatus = state.mstatus & mask;
 536       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 537           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 538         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 539       return sstatus;
 540     }
 541     case CSR_SIP: return state.mip & state.mideleg;
 542     case CSR_SIE: return state.mie & state.mideleg;
 543     case CSR_SEPC: return state.sepc;
 544     case CSR_SBADADDR: return state.sbadaddr;
 545     case CSR_STVEC: return state.stvec;
 546     case CSR_SCAUSE:
 547       if (max_xlen > xlen)
 548         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 549       return state.scause;
 550     case CSR_SPTBR:
 551       if (get_field(state.mstatus, MSTATUS_TVM))
 552         require_privilege(PRV_M);
 553       return state.sptbr;
 554     case CSR_SSCRATCH: return state.sscratch;
 555     case CSR_MSTATUS: return state.mstatus;
 556     case CSR_MIP: return state.mip;
 557     case CSR_MIE: return state.mie;
 558     case CSR_MEPC: return state.mepc;
 559     case CSR_MSCRATCH: return state.mscratch;
 560     case CSR_MCAUSE: return state.mcause;
 561     case CSR_MBADADDR: return state.mbadaddr;
 562     case CSR_MISA: return isa;
 563     case CSR_MARCHID: return 0;
 564     case CSR_MIMPID: return 0;
 565     case CSR_MVENDORID: return 0;
 566     case CSR_MHARTID: return id;
 567     case CSR_MTVEC: return state.mtvec;
 568     case CSR_MEDELEG: return state.medeleg;
 569     case CSR_MIDELEG: return state.mideleg;
 570     case CSR_TSELECT: return state.tselect;
 571     case CSR_TDATA1:
 572       if (state.tselect < state.num_triggers) {
 573         reg_t v = 0;
 574         mcontrol_t *mc = &state.mcontrol[state.tselect];
 575         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 576         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 577         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 578         v = set_field(v, MCONTROL_SELECT, mc->select);
 579         v = set_field(v, MCONTROL_TIMING, mc->timing);
 580         v = set_field(v, MCONTROL_ACTION, mc->action);
 581         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 582         v = set_field(v, MCONTROL_MATCH, mc->match);
 583         v = set_field(v, MCONTROL_M, mc->m);
 584         v = set_field(v, MCONTROL_H, mc->h);
 585         v = set_field(v, MCONTROL_S, mc->s);
 586         v = set_field(v, MCONTROL_U, mc->u);
 587         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 588         v = set_field(v, MCONTROL_STORE, mc->store);
 589         v = set_field(v, MCONTROL_LOAD, mc->load);
 590         return v;
 591       } else {
 592         return 0;
 593       }
 594       break;
 595     case CSR_TDATA2:
 596       if (state.tselect < state.num_triggers) {
 597         return state.tdata2[state.tselect];
 598       } else {
 599         return 0;
 600       }
 601       break;
 602     case CSR_TDATA3: return 0;
 603     case CSR_DCSR:
 604       {
 605         uint32_t v = 0;
 606         v = set_field(v, DCSR_XDEBUGVER, 1);
 607         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 608         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 609         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 610         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 611         v = set_field(v, DCSR_STOPCYCLE, 0);
 612         v = set_field(v, DCSR_STOPTIME, 0);
 613         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 614         v = set_field(v, DCSR_STEP, state.dcsr.step);
 615         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 616         return v;
 617       }
 618     case CSR_DPC:
 619       return state.dpc;
 620     case CSR_DSCRATCH:
 621       return state.dscratch;
 622   }
 623   throw trap_illegal_instruction(0);
 624 }
 625
 626 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 627 {
 628   throw trap_illegal_instruction(0);
 629 }
 630
 631 insn_func_t processor_t::decode_insn(insn_t insn)
 632 {
 633   // look up opcode in hash table
 634   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 635   insn_desc_t desc = opcode_cache[idx];
 636
 637   if (unlikely(insn.bits() != desc.match)) {
 638     // fall back to linear search
 639     insn_desc_t* p = &instructions[0];
 640     while ((insn.bits() & p->mask) != p->match)
 641       p++;
 642     desc = *p;
 643
 644     if (p->mask != 0 && p > &instructions[0]) {
 645       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 646         // move to front of opcode list to reduce miss penalty
 647         while (--p >= &instructions[0])
 648           *(p+1) = *p;
 649         instructions[0] = desc;
 650       }
 651     }
 652
 653     opcode_cache[idx] = desc;
 654     opcode_cache[idx].match = insn.bits();
 655   }
 656
 657   return xlen == 64 ? desc.rv64 : desc.rv32;
 658 }
 659
 660 void processor_t::register_insn(insn_desc_t desc)
 661 {
 662   instructions.push_back(desc);
 663 }
 664
 665 void processor_t::build_opcode_map()
 666 {
 667   struct cmp {
 668     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 669       if (lhs.match == rhs.match)
 670         return lhs.mask > rhs.mask;
 671       return lhs.match > rhs.match;
 672     }
 673   };
 674   std::sort(instructions.begin(), instructions.end(), cmp());
 675
 676   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 677     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 678 }
 679
 680 void processor_t::register_extension(extension_t* x)
 681 {
 682   for (auto insn : x->get_instructions())
 683     register_insn(insn);
 684   build_opcode_map();
 685   for (auto disasm_insn : x->get_disasms())
 686     disassembler->add_insn(disasm_insn);
 687   if (ext != NULL)
 688     throw std::logic_error("only one extension may be registered");
 689   ext = x;
 690   x->set_processor(this);
 691 }
 692
 693 void processor_t::register_base_instructions()
 694 {
 695   #define DECLARE_INSN(name, match, mask) \
 696     insn_bits_t name##_match = (match), name##_mask = (mask);
 697   #include "encoding.h"
 698   #undef DECLARE_INSN
 699
 700   #define DEFINE_INSN(name) \
 701     REGISTER_INSN(this, name, name##_match, name##_mask)
 702   #include "insn_list.h"
 703   #undef DEFINE_INSN
 704
 705   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 706   build_opcode_map();
 707 }
 708
 709 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 710 {
 711   switch (addr)
 712   {
 713     case 0:
 714       if (len <= 4) {
 715         memset(bytes, 0, len);
 716         bytes[0] = get_field(state.mip, MIP_MSIP);
 717         return true;
 718       }
 719       break;
 720   }
 721
 722   return false;
 723 }
 724
 725 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 726 {
 727   switch (addr)
 728   {
 729     case 0:
 730       if (len <= 4) {
 731         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 732         return true;
 733       }
 734       break;
 735   }
 736
 737   return false;
 738 }
 739
 740 void processor_t::trigger_updated()
 741 {
 742   mmu->flush_tlb();
 743   mmu->check_triggers_fetch = false;
 744   mmu->check_triggers_load = false;
 745   mmu->check_triggers_store = false;
 746
 747   for (unsigned i = 0; i < state.num_triggers; i++) {
 748     if (state.mcontrol[i].execute) {
 749       mmu->check_triggers_fetch = true;
 750     }
 751     if (state.mcontrol[i].load) {
 752       mmu->check_triggers_load = true;
 753     }
 754     if (state.mcontrol[i].store) {
 755       mmu->check_triggers_store = true;
 756     }
 757   }
 758 }