riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa = "rv" + std::to_string(max_xlen) + p;
  86   cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     cpuid |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107 }
 108
 109 void state_t::reset()
 110 {
 111   memset(this, 0, sizeof(*this));
 112   prv = PRV_M;
 113   pc = DEFAULT_RSTVEC;
 114   load_reservation = -1;
 115 }
 116
 117 void processor_t::set_debug(bool value)
 118 {
 119   debug = value;
 120   if (ext)
 121     ext->set_debug(value);
 122 }
 123
 124 void processor_t::set_histogram(bool value)
 125 {
 126   histogram_enabled = value;
 127 #ifndef RISCV_ENABLE_HISTOGRAM
 128   if (value) {
 129     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 130     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 131   }
 132 #endif
 133 }
 134
 135 void processor_t::reset(bool value)
 136 {
 137   if (run == !value)
 138     return;
 139   run = !value;
 140
 141   state.reset();
 142   set_csr(CSR_MSTATUS, state.mstatus);
 143
 144   if (ext)
 145     ext->reset(); // reset the extension
 146 }
 147
 148 void processor_t::raise_interrupt(reg_t which)
 149 {
 150   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 151 }
 152
 153 static int ctz(reg_t val)
 154 {
 155   int res = 0;
 156   if (val)
 157     while ((val & 1) == 0)
 158       val >>= 1, res++;
 159   return res;
 160 }
 161
 162 void processor_t::take_interrupt()
 163 {
 164   check_timer();
 165
 166   reg_t interrupts = state.mip & state.mie;
 167
 168   reg_t m_interrupts = interrupts & ~state.mideleg;
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
 171     raise_interrupt(ctz(m_interrupts));
 172
 173   reg_t s_interrupts = interrupts & state.mideleg;
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
 176     raise_interrupt(ctz(s_interrupts));
 177 }
 178
 179 void processor_t::check_timer()
 180 {
 181   if (sim->rtc >= state.mtimecmp)
 182     state.mip |= MIP_MTIP;
 183 }
 184
 185 static bool validate_priv(reg_t priv)
 186 {
 187   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 188 }
 189
 190 void processor_t::set_privilege(reg_t prv)
 191 {
 192   assert(validate_priv(prv));
 193   mmu->flush_tlb();
 194   state.prv = prv;
 195 }
 196
 197 void processor_t::take_trap(trap_t& t, reg_t epc)
 198 {
 199   if (debug)
 200     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 201             id, t.name(), epc);
 202
 203   // by default, trap to M-mode, unless delegated to S-mode
 204   reg_t bit = t.cause();
 205   reg_t deleg = state.medeleg;
 206   if (bit & ((reg_t)1 << (max_xlen-1)))
 207     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 208   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 209     // handle the trap in S-mode
 210     state.pc = state.stvec;
 211     state.scause = t.cause();
 212     state.sepc = epc;
 213     if (t.has_badaddr())
 214       state.sbadaddr = t.get_badaddr();
 215
 216     reg_t s = state.mstatus;
 217     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 218     s = set_field(s, MSTATUS_SPP, state.prv);
 219     s = set_field(s, MSTATUS_SIE, 0);
 220     set_csr(CSR_MSTATUS, s);
 221     set_privilege(PRV_S);
 222   } else {
 223     state.pc = DEFAULT_MTVEC;
 224     state.mcause = t.cause();
 225     state.mepc = epc;
 226     if (t.has_badaddr())
 227       state.mbadaddr = t.get_badaddr();
 228
 229     reg_t s = state.mstatus;
 230     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 231     s = set_field(s, MSTATUS_MPP, state.prv);
 232     s = set_field(s, MSTATUS_MIE, 0);
 233     set_csr(CSR_MSTATUS, s);
 234     set_privilege(PRV_M);
 235   }
 236
 237   yield_load_reservation();
 238 }
 239
 240 void processor_t::disasm(insn_t insn)
 241 {
 242   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 243   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 244           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 245 }
 246
 247 static bool validate_vm(int max_xlen, reg_t vm)
 248 {
 249   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 250     return true;
 251   if (max_xlen == 32 && vm == VM_SV32)
 252     return true;
 253   return vm == VM_MBARE;
 254 }
 255
 256 void processor_t::set_csr(int which, reg_t val)
 257 {
 258   val = zext_xlen(val);
 259   reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
 260   reg_t s_ints = MIP_SSIP | MIP_STIP;
 261   switch (which)
 262   {
 263     case CSR_FFLAGS:
 264       dirty_fp_state;
 265       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 266       break;
 267     case CSR_FRM:
 268       dirty_fp_state;
 269       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 270       break;
 271     case CSR_FCSR:
 272       dirty_fp_state;
 273       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 274       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 275       break;
 276     case CSR_MTIME:
 277     case CSR_STIMEW:
 278       // this implementation ignores writes to MTIME
 279       break;
 280     case CSR_MTIMEH:
 281     case CSR_STIMEHW:
 282       // this implementation ignores writes to MTIME
 283       break;
 284     case CSR_TIMEW:
 285       val -= sim->rtc;
 286       if (xlen == 32)
 287         state.sutime_delta = val | (state.sutime_delta >> 32 << 32);
 288       else
 289         state.sutime_delta = val;
 290       break;
 291     case CSR_TIMEHW:
 292       val = ((val << 32) - sim->rtc) >> 32;
 293       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 294       break;
 295     case CSR_CYCLEW:
 296     case CSR_INSTRETW:
 297       val -= state.minstret;
 298       if (xlen == 32)
 299         state.suinstret_delta = val | (state.suinstret_delta >> 32 << 32);
 300       else
 301         state.suinstret_delta = val;
 302       break;
 303     case CSR_CYCLEHW:
 304     case CSR_INSTRETHW:
 305       val = ((val << 32) - state.minstret) >> 32;
 306       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 307       break;
 308     case CSR_MSTATUS: {
 309       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV))
 310         mmu->flush_tlb();
 311
 312       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 313                  | MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_FS
 314                  | (ext ? MSTATUS_XS : 0);
 315
 316       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 317         mask |= MSTATUS_VM;
 318       if (validate_priv(get_field(val, MSTATUS_MPP)))
 319         mask |= MSTATUS_MPP;
 320
 321       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 322
 323       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 324       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 325       if (max_xlen == 32)
 326         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 327       else
 328         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 329
 330       // spike supports the notion of xlen < max_xlen, but current priv spec
 331       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 332       xlen = max_xlen;
 333       break;
 334     }
 335     case CSR_MIP: {
 336       reg_t mask = all_ints &~ MIP_MTIP;
 337       state.mip = (state.mip & ~mask) | (val & mask);
 338       break;
 339     }
 340     case CSR_MIPI:
 341       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 342       break;
 343     case CSR_MIE:
 344       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 345       break;
 346     case CSR_MIDELEG:
 347       state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
 348       break;
 349     case CSR_MEDELEG: {
 350       reg_t mask = 0;
 351 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 352 #include "encoding.h"
 353 #undef DECLARE_CAUSE
 354       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 355       break;
 356     }
 357     case CSR_SSTATUS: {
 358       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 359                  | SSTATUS_XS;
 360       set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 361       break;
 362     }
 363     case CSR_SIP: {
 364       reg_t mask = s_ints &~ MIP_STIP;
 365       state.mip = (state.mip & ~mask) | (val & mask);
 366       break;
 367     }
 368     case CSR_SIE: {
 369       reg_t mask = s_ints;
 370       state.mie = (state.mie & ~mask) | (val & mask);
 371       break;
 372     }
 373     case CSR_SEPC: state.sepc = val; break;
 374     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 375     case CSR_SPTBR: state.sptbr = val & -PGSIZE; break;
 376     case CSR_SSCRATCH: state.sscratch = val; break;
 377     case CSR_SCAUSE: state.scause = val; break;
 378     case CSR_SBADADDR: state.sbadaddr = val; break;
 379     case CSR_MEPC: state.mepc = val; break;
 380     case CSR_MSCRATCH: state.mscratch = val; break;
 381     case CSR_MCAUSE: state.mcause = val; break;
 382     case CSR_MBADADDR: state.mbadaddr = val; break;
 383     case CSR_MTIMECMP:
 384       state.mip &= ~MIP_MTIP;
 385       state.mtimecmp = val;
 386       break;
 387     case CSR_MTOHOST:
 388       if (state.tohost == 0)
 389         state.tohost = val;
 390       break;
 391     case CSR_MFROMHOST:
 392       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 393       state.fromhost = val;
 394       break;
 395   }
 396 }
 397
 398 reg_t processor_t::get_csr(int which)
 399 {
 400   switch (which)
 401   {
 402     case CSR_FFLAGS:
 403       require_fp;
 404       if (!supports_extension('F'))
 405         break;
 406       return state.fflags;
 407     case CSR_FRM:
 408       require_fp;
 409       if (!supports_extension('F'))
 410         break;
 411       return state.frm;
 412     case CSR_FCSR:
 413       require_fp;
 414       if (!supports_extension('F'))
 415         break;
 416       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 417     case CSR_MTIME:
 418     case CSR_STIME:
 419     case CSR_STIMEW:
 420       return sim->rtc;
 421     case CSR_MTIMEH:
 422     case CSR_STIMEH:
 423     case CSR_STIMEHW:
 424       return sim->rtc >> 32;
 425     case CSR_TIME:
 426     case CSR_TIMEW:
 427       return sim->rtc + state.sutime_delta;
 428     case CSR_CYCLE:
 429     case CSR_CYCLEW:
 430     case CSR_INSTRET:
 431     case CSR_INSTRETW:
 432       return state.minstret + state.suinstret_delta;
 433     case CSR_TIMEH:
 434     case CSR_TIMEHW:
 435       if (xlen == 64)
 436         break;
 437       return (sim->rtc + state.sutime_delta) >> 32;
 438     case CSR_CYCLEH:
 439     case CSR_INSTRETH:
 440     case CSR_CYCLEHW:
 441     case CSR_INSTRETHW:
 442       if (xlen == 64)
 443         break;
 444       return (state.minstret + state.suinstret_delta) >> 32;
 445     case CSR_SSTATUS: {
 446       reg_t sstatus = state.mstatus &
 447         (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS);
 448       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 449           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 450         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 451       return sstatus;
 452     }
 453     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 454     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 455     case CSR_SEPC: return state.sepc;
 456     case CSR_SBADADDR: return state.sbadaddr;
 457     case CSR_STVEC: return state.stvec;
 458     case CSR_SCAUSE:
 459       if (max_xlen > xlen)
 460         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 461       return state.scause;
 462     case CSR_SPTBR: return state.sptbr;
 463     case CSR_SASID: return 0;
 464     case CSR_SSCRATCH: return state.sscratch;
 465     case CSR_MSTATUS: return state.mstatus;
 466     case CSR_MIP: return state.mip;
 467     case CSR_MIPI: return 0;
 468     case CSR_MIE: return state.mie;
 469     case CSR_MEPC: return state.mepc;
 470     case CSR_MSCRATCH: return state.mscratch;
 471     case CSR_MCAUSE: return state.mcause;
 472     case CSR_MBADADDR: return state.mbadaddr;
 473     case CSR_MTIMECMP: return state.mtimecmp;
 474     case CSR_MCPUID: return cpuid;
 475     case CSR_MIMPID: return IMPL_ROCKET;
 476     case CSR_MHARTID: return id;
 477     case CSR_MTVEC: return DEFAULT_MTVEC;
 478     case CSR_MEDELEG: return state.medeleg;
 479     case CSR_MIDELEG: return state.mideleg;
 480     case CSR_MTOHOST:
 481       sim->get_htif()->tick(); // not necessary, but faster
 482       return state.tohost;
 483     case CSR_MFROMHOST:
 484       sim->get_htif()->tick(); // not necessary, but faster
 485       return state.fromhost;
 486     case CSR_MIOBASE: return sim->memsz;
 487     case CSR_UARCH0:
 488     case CSR_UARCH1:
 489     case CSR_UARCH2:
 490     case CSR_UARCH3:
 491     case CSR_UARCH4:
 492     case CSR_UARCH5:
 493     case CSR_UARCH6:
 494     case CSR_UARCH7:
 495     case CSR_UARCH8:
 496     case CSR_UARCH9:
 497     case CSR_UARCH10:
 498     case CSR_UARCH11:
 499     case CSR_UARCH12:
 500     case CSR_UARCH13:
 501     case CSR_UARCH14:
 502     case CSR_UARCH15:
 503       return 0;
 504   }
 505   throw trap_illegal_instruction();
 506 }
 507
 508 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 509 {
 510   throw trap_illegal_instruction();
 511 }
 512
 513 insn_func_t processor_t::decode_insn(insn_t insn)
 514 {
 515   // look up opcode in hash table
 516   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 517   insn_desc_t desc = opcode_cache[idx];
 518
 519   if (unlikely(insn.bits() != desc.match)) {
 520     // fall back to linear search
 521     insn_desc_t* p = &instructions[0];
 522     while ((insn.bits() & p->mask) != p->match)
 523       p++;
 524     desc = *p;
 525
 526     if (p->mask != 0 && p > &instructions[0]) {
 527       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 528         // move to front of opcode list to reduce miss penalty
 529         while (--p >= &instructions[0])
 530           *(p+1) = *p;
 531         instructions[0] = desc;
 532       }
 533     }
 534
 535     opcode_cache[idx] = desc;
 536     opcode_cache[idx].match = insn.bits();
 537   }
 538
 539   return xlen == 64 ? desc.rv64 : desc.rv32;
 540 }
 541
 542 void processor_t::register_insn(insn_desc_t desc)
 543 {
 544   instructions.push_back(desc);
 545 }
 546
 547 void processor_t::build_opcode_map()
 548 {
 549   struct cmp {
 550     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 551       if (lhs.match == rhs.match)
 552         return lhs.mask > rhs.mask;
 553       return lhs.match > rhs.match;
 554     }
 555   };
 556   std::sort(instructions.begin(), instructions.end(), cmp());
 557
 558   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 559     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 560 }
 561
 562 void processor_t::register_extension(extension_t* x)
 563 {
 564   for (auto insn : x->get_instructions())
 565     register_insn(insn);
 566   build_opcode_map();
 567   for (auto disasm_insn : x->get_disasms())
 568     disassembler->add_insn(disasm_insn);
 569   if (ext != NULL)
 570     throw std::logic_error("only one extension may be registered");
 571   ext = x;
 572   x->set_processor(this);
 573 }
 574
 575 void processor_t::register_base_instructions()
 576 {
 577   #define DECLARE_INSN(name, match, mask) \
 578     insn_bits_t name##_match = (match), name##_mask = (mask);
 579   #include "encoding.h"
 580   #undef DECLARE_INSN
 581
 582   #define DEFINE_INSN(name) \
 583     REGISTER_INSN(this, name, name##_match, name##_mask)
 584   #include "insn_list.h"
 585   #undef DEFINE_INSN
 586
 587   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 588   build_opcode_map();
 589 }
 590
 591 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 592 {
 593   try {
 594     auto res = get_csr(addr / (max_xlen / 8));
 595     memcpy(bytes, &res, len);
 596     return true;
 597   } catch (trap_illegal_instruction& t) {
 598     return false;
 599   }
 600 }
 601
 602 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 603 {
 604   try {
 605     reg_t value = 0;
 606     memcpy(&value, bytes, len);
 607     set_csr(addr / (max_xlen / 8), value);
 608     return true;
 609   } catch (trap_illegal_instruction& t) {
 610     return false;
 611   }
 612 }