riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   fprintf(stderr, "Entering debug mode because of cause %d", cause);
 193   state.dcsr.cause = cause;
 194   state.dcsr.prv = state.prv;
 195   set_privilege(PRV_M);
 196   state.dpc = state.pc;
 197   state.pc = debug_rom_entry();
 198 }
 199
 200 void processor_t::take_trap(trap_t& t, reg_t epc)
 201 {
 202   if (debug) {
 203     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 204             id, t.name(), epc);
 205     if (t.has_badaddr())
 206       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 207           t.get_badaddr());
 208   }
 209
 210   if (state.dcsr.cause) {
 211     if (t.cause() == CAUSE_BREAKPOINT) {
 212       state.pc = debug_rom_entry();
 213     } else {
 214       state.pc = DEBUG_ROM_TVEC;
 215     }
 216     return;
 217   }
 218
 219   if (t.cause() == CAUSE_BREAKPOINT && (
 220               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 221               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 222               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 223               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 224     enter_debug_mode(DCSR_CAUSE_SWBP);
 225     return;
 226   }
 227
 228   // by default, trap to M-mode, unless delegated to S-mode
 229   reg_t bit = t.cause();
 230   reg_t deleg = state.medeleg;
 231   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 232   if (interrupt)
 233     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 234   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 235     // handle the trap in S-mode
 236     state.pc = state.stvec;
 237     state.scause = t.cause();
 238     state.sepc = epc;
 239     if (t.has_badaddr())
 240       state.sbadaddr = t.get_badaddr();
 241
 242     reg_t s = state.mstatus;
 243     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 244     s = set_field(s, MSTATUS_SPP, state.prv);
 245     s = set_field(s, MSTATUS_SIE, 0);
 246     set_csr(CSR_MSTATUS, s);
 247     set_privilege(PRV_S);
 248   } else {
 249     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 250     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 251     state.mepc = epc;
 252     state.mcause = t.cause();
 253     if (t.has_badaddr())
 254       state.mbadaddr = t.get_badaddr();
 255
 256     reg_t s = state.mstatus;
 257     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 258     s = set_field(s, MSTATUS_MPP, state.prv);
 259     s = set_field(s, MSTATUS_MIE, 0);
 260     set_csr(CSR_MSTATUS, s);
 261     set_privilege(PRV_M);
 262   }
 263
 264   yield_load_reservation();
 265 }
 266
 267 void processor_t::disasm(insn_t insn)
 268 {
 269   static uint64_t last_pc = 1, last_bits;
 270   static uint64_t executions = 1;
 271
 272   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 273   if (last_pc != state.pc || last_bits != bits) {
 274     if (executions != 1) {
 275       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 276     }
 277
 278     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 279             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 280     last_pc = state.pc;
 281     last_bits = bits;
 282     executions = 1;
 283   } else {
 284     executions++;
 285   }
 286 }
 287
 288 int processor_t::paddr_bits()
 289 {
 290   assert(xlen == max_xlen);
 291   return max_xlen == 64 ? 50 : 34;
 292 }
 293
 294 void processor_t::set_csr(int which, reg_t val)
 295 {
 296   val = zext_xlen(val);
 297   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 298   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 299   switch (which)
 300   {
 301     case CSR_FFLAGS:
 302       dirty_fp_state;
 303       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 304       break;
 305     case CSR_FRM:
 306       dirty_fp_state;
 307       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 308       break;
 309     case CSR_FCSR:
 310       dirty_fp_state;
 311       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 312       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 313       break;
 314     case CSR_MSTATUS: {
 315       if ((val ^ state.mstatus) &
 316           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 317         mmu->flush_tlb();
 318
 319       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 320                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 321                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 322                  | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
 323
 324       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 325
 326       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 327       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 328       if (max_xlen == 32)
 329         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 330       else
 331         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 332
 333       // spike supports the notion of xlen < max_xlen, but current priv spec
 334       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 335       xlen = max_xlen;
 336       break;
 337     }
 338     case CSR_MIP: {
 339       reg_t mask = MIP_SSIP | MIP_STIP;
 340       state.mip = (state.mip & ~mask) | (val & mask);
 341       break;
 342     }
 343     case CSR_MIE:
 344       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 345       break;
 346     case CSR_MIDELEG:
 347       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 348       break;
 349     case CSR_MEDELEG: {
 350       reg_t mask = 0;
 351 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 352 #include "encoding.h"
 353 #undef DECLARE_CAUSE
 354       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 355       break;
 356     }
 357     case CSR_MINSTRET:
 358     case CSR_MCYCLE:
 359       if (xlen == 32)
 360         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 361       else
 362         state.minstret = val;
 363       break;
 364     case CSR_MINSTRETH:
 365     case CSR_MCYCLEH:
 366       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 367       break;
 368     case CSR_SCOUNTEREN:
 369       state.scounteren = val;
 370       break;
 371     case CSR_MCOUNTEREN:
 372       state.mcounteren = val;
 373       break;
 374     case CSR_SSTATUS: {
 375       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 376                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 377       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 378     }
 379     case CSR_SIP: {
 380       reg_t mask = MIP_SSIP & state.mideleg;
 381       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 382     }
 383     case CSR_SIE:
 384       return set_csr(CSR_MIE,
 385                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 386     case CSR_SPTBR: {
 387       mmu->flush_tlb();
 388       if (max_xlen == 32)
 389         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 390       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 391                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 392                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 393         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 394       break;
 395     }
 396     case CSR_SEPC: state.sepc = val; break;
 397     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 398     case CSR_SSCRATCH: state.sscratch = val; break;
 399     case CSR_SCAUSE: state.scause = val; break;
 400     case CSR_SBADADDR: state.sbadaddr = val; break;
 401     case CSR_MEPC: state.mepc = val; break;
 402     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 403     case CSR_MSCRATCH: state.mscratch = val; break;
 404     case CSR_MCAUSE: state.mcause = val; break;
 405     case CSR_MBADADDR: state.mbadaddr = val; break;
 406     case CSR_MISA: {
 407       if (!(val & (1L << ('F' - 'A'))))
 408         val &= ~(1L << ('D' - 'A'));
 409
 410       // allow MAFDC bits in MISA to be modified
 411       reg_t mask = 0;
 412       mask |= 1L << ('M' - 'A');
 413       mask |= 1L << ('A' - 'A');
 414       mask |= 1L << ('F' - 'A');
 415       mask |= 1L << ('D' - 'A');
 416       mask |= 1L << ('C' - 'A');
 417       mask &= max_isa;
 418
 419       isa = (val & mask) | (isa & ~mask);
 420       break;
 421     }
 422     case CSR_TSELECT:
 423       if (val < state.num_triggers) {
 424         state.tselect = val;
 425       }
 426       break;
 427     case CSR_TDATA1:
 428       {
 429         mcontrol_t *mc = &state.mcontrol[state.tselect];
 430         if (mc->dmode && !state.dcsr.cause) {
 431           break;
 432         }
 433         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 434         mc->select = get_field(val, MCONTROL_SELECT);
 435         mc->timing = get_field(val, MCONTROL_TIMING);
 436         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 437         mc->chain = get_field(val, MCONTROL_CHAIN);
 438         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 439         mc->m = get_field(val, MCONTROL_M);
 440         mc->h = get_field(val, MCONTROL_H);
 441         mc->s = get_field(val, MCONTROL_S);
 442         mc->u = get_field(val, MCONTROL_U);
 443         mc->execute = get_field(val, MCONTROL_EXECUTE);
 444         mc->store = get_field(val, MCONTROL_STORE);
 445         mc->load = get_field(val, MCONTROL_LOAD);
 446         // Assume we're here because of csrw.
 447         if (mc->execute)
 448           mc->timing = 0;
 449         trigger_updated();
 450       }
 451       break;
 452     case CSR_TDATA2:
 453       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 454         break;
 455       }
 456       if (state.tselect < state.num_triggers) {
 457         state.tdata2[state.tselect] = val;
 458       }
 459       break;
 460     case CSR_DCSR:
 461       state.dcsr.prv = get_field(val, DCSR_PRV);
 462       state.dcsr.step = get_field(val, DCSR_STEP);
 463       // TODO: ndreset and fullreset
 464       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 465       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 466       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 467       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 468       state.dcsr.halt = get_field(val, DCSR_HALT);
 469       break;
 470     case CSR_DPC:
 471       state.dpc = val;
 472       break;
 473     case CSR_DSCRATCH:
 474       state.dscratch = val;
 475       break;
 476   }
 477 }
 478
 479 reg_t processor_t::get_csr(int which)
 480 {
 481   uint32_t ctr_en = -1;
 482   if (state.prv < PRV_M)
 483     ctr_en &= state.mcounteren;
 484   if (state.prv < PRV_S)
 485     ctr_en &= state.scounteren;
 486   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 487
 488   if (ctr_ok) {
 489     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 490       return 0;
 491     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 492       return 0;
 493   }
 494   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 495     return 0;
 496   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 497     return 0;
 498   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 499     return 0;
 500
 501   switch (which)
 502   {
 503     case CSR_FFLAGS:
 504       require_fp;
 505       if (!supports_extension('F'))
 506         break;
 507       return state.fflags;
 508     case CSR_FRM:
 509       require_fp;
 510       if (!supports_extension('F'))
 511         break;
 512       return state.frm;
 513     case CSR_FCSR:
 514       require_fp;
 515       if (!supports_extension('F'))
 516         break;
 517       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 518     case CSR_INSTRET:
 519     case CSR_CYCLE:
 520       if (ctr_ok)
 521         return state.minstret;
 522       break;
 523     case CSR_MINSTRET:
 524     case CSR_MCYCLE:
 525       return state.minstret;
 526     case CSR_MINSTRETH:
 527     case CSR_MCYCLEH:
 528       if (xlen == 32)
 529         return state.minstret >> 32;
 530       break;
 531     case CSR_SCOUNTEREN: return state.scounteren;
 532     case CSR_MCOUNTEREN: return state.mcounteren;
 533     case CSR_SSTATUS: {
 534       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 535                  | SSTATUS_XS | SSTATUS_SUM;
 536       reg_t sstatus = state.mstatus & mask;
 537       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 538           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 539         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 540       return sstatus;
 541     }
 542     case CSR_SIP: return state.mip & state.mideleg;
 543     case CSR_SIE: return state.mie & state.mideleg;
 544     case CSR_SEPC: return state.sepc;
 545     case CSR_SBADADDR: return state.sbadaddr;
 546     case CSR_STVEC: return state.stvec;
 547     case CSR_SCAUSE:
 548       if (max_xlen > xlen)
 549         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 550       return state.scause;
 551     case CSR_SPTBR:
 552       if (get_field(state.mstatus, MSTATUS_TVM))
 553         require_privilege(PRV_M);
 554       return state.sptbr;
 555     case CSR_SSCRATCH: return state.sscratch;
 556     case CSR_MSTATUS: return state.mstatus;
 557     case CSR_MIP: return state.mip;
 558     case CSR_MIE: return state.mie;
 559     case CSR_MEPC: return state.mepc;
 560     case CSR_MSCRATCH: return state.mscratch;
 561     case CSR_MCAUSE: return state.mcause;
 562     case CSR_MBADADDR: return state.mbadaddr;
 563     case CSR_MISA: return isa;
 564     case CSR_MARCHID: return 0;
 565     case CSR_MIMPID: return 0;
 566     case CSR_MVENDORID: return 0;
 567     case CSR_MHARTID: return id;
 568     case CSR_MTVEC: return state.mtvec;
 569     case CSR_MEDELEG: return state.medeleg;
 570     case CSR_MIDELEG: return state.mideleg;
 571     case CSR_TSELECT: return state.tselect;
 572     case CSR_TDATA1:
 573       if (state.tselect < state.num_triggers) {
 574         reg_t v = 0;
 575         mcontrol_t *mc = &state.mcontrol[state.tselect];
 576         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 577         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 578         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 579         v = set_field(v, MCONTROL_SELECT, mc->select);
 580         v = set_field(v, MCONTROL_TIMING, mc->timing);
 581         v = set_field(v, MCONTROL_ACTION, mc->action);
 582         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 583         v = set_field(v, MCONTROL_MATCH, mc->match);
 584         v = set_field(v, MCONTROL_M, mc->m);
 585         v = set_field(v, MCONTROL_H, mc->h);
 586         v = set_field(v, MCONTROL_S, mc->s);
 587         v = set_field(v, MCONTROL_U, mc->u);
 588         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 589         v = set_field(v, MCONTROL_STORE, mc->store);
 590         v = set_field(v, MCONTROL_LOAD, mc->load);
 591         return v;
 592       } else {
 593         return 0;
 594       }
 595       break;
 596     case CSR_TDATA2:
 597       if (state.tselect < state.num_triggers) {
 598         return state.tdata2[state.tselect];
 599       } else {
 600         return 0;
 601       }
 602       break;
 603     case CSR_TDATA3: return 0;
 604     case CSR_DCSR:
 605       {
 606         uint32_t v = 0;
 607         v = set_field(v, DCSR_XDEBUGVER, 1);
 608         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 609         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 610         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 611         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 612         v = set_field(v, DCSR_STOPCYCLE, 0);
 613         v = set_field(v, DCSR_STOPTIME, 0);
 614         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 615         v = set_field(v, DCSR_STEP, state.dcsr.step);
 616         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 617         return v;
 618       }
 619     case CSR_DPC:
 620       return state.dpc;
 621     case CSR_DSCRATCH:
 622       return state.dscratch;
 623   }
 624   throw trap_illegal_instruction(0);
 625 }
 626
 627 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 628 {
 629   throw trap_illegal_instruction(0);
 630 }
 631
 632 insn_func_t processor_t::decode_insn(insn_t insn)
 633 {
 634   // look up opcode in hash table
 635   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 636   insn_desc_t desc = opcode_cache[idx];
 637
 638   if (unlikely(insn.bits() != desc.match)) {
 639     // fall back to linear search
 640     insn_desc_t* p = &instructions[0];
 641     while ((insn.bits() & p->mask) != p->match)
 642       p++;
 643     desc = *p;
 644
 645     if (p->mask != 0 && p > &instructions[0]) {
 646       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 647         // move to front of opcode list to reduce miss penalty
 648         while (--p >= &instructions[0])
 649           *(p+1) = *p;
 650         instructions[0] = desc;
 651       }
 652     }
 653
 654     opcode_cache[idx] = desc;
 655     opcode_cache[idx].match = insn.bits();
 656   }
 657
 658   return xlen == 64 ? desc.rv64 : desc.rv32;
 659 }
 660
 661 void processor_t::register_insn(insn_desc_t desc)
 662 {
 663   instructions.push_back(desc);
 664 }
 665
 666 void processor_t::build_opcode_map()
 667 {
 668   struct cmp {
 669     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 670       if (lhs.match == rhs.match)
 671         return lhs.mask > rhs.mask;
 672       return lhs.match > rhs.match;
 673     }
 674   };
 675   std::sort(instructions.begin(), instructions.end(), cmp());
 676
 677   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 678     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 679 }
 680
 681 void processor_t::register_extension(extension_t* x)
 682 {
 683   for (auto insn : x->get_instructions())
 684     register_insn(insn);
 685   build_opcode_map();
 686   for (auto disasm_insn : x->get_disasms())
 687     disassembler->add_insn(disasm_insn);
 688   if (ext != NULL)
 689     throw std::logic_error("only one extension may be registered");
 690   ext = x;
 691   x->set_processor(this);
 692 }
 693
 694 void processor_t::register_base_instructions()
 695 {
 696   #define DECLARE_INSN(name, match, mask) \
 697     insn_bits_t name##_match = (match), name##_mask = (mask);
 698   #include "encoding.h"
 699   #undef DECLARE_INSN
 700
 701   #define DEFINE_INSN(name) \
 702     REGISTER_INSN(this, name, name##_match, name##_mask)
 703   #include "insn_list.h"
 704   #undef DEFINE_INSN
 705
 706   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 707   build_opcode_map();
 708 }
 709
 710 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 711 {
 712   switch (addr)
 713   {
 714     case 0:
 715       if (len <= 4) {
 716         memset(bytes, 0, len);
 717         bytes[0] = get_field(state.mip, MIP_MSIP);
 718         return true;
 719       }
 720       break;
 721   }
 722
 723   return false;
 724 }
 725
 726 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 727 {
 728   switch (addr)
 729   {
 730     case 0:
 731       if (len <= 4) {
 732         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 733         return true;
 734       }
 735       break;
 736   }
 737
 738   return false;
 739 }
 740
 741 void processor_t::trigger_updated()
 742 {
 743   mmu->flush_tlb();
 744   mmu->check_triggers_fetch = false;
 745   mmu->check_triggers_load = false;
 746   mmu->check_triggers_store = false;
 747
 748   for (unsigned i = 0; i < state.num_triggers; i++) {
 749     if (state.mcontrol[i].execute) {
 750       mmu->check_triggers_fetch = true;
 751     }
 752     if (state.mcontrol[i].load) {
 753       mmu->check_triggers_load = true;
 754     }
 755     if (state.mcontrol[i].store) {
 756       mmu->check_triggers_store = true;
 757     }
 758   }
 759 }