riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   load_reservation = -1;
 119 }
 120
 121 void processor_t::set_debug(bool value)
 122 {
 123   debug = value;
 124   if (ext)
 125     ext->set_debug(value);
 126 }
 127
 128 void processor_t::set_histogram(bool value)
 129 {
 130   histogram_enabled = value;
 131 #ifndef RISCV_ENABLE_HISTOGRAM
 132   if (value) {
 133     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 134     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 135   }
 136 #endif
 137 }
 138
 139 void processor_t::reset(bool value)
 140 {
 141   if (run == !value)
 142     return;
 143   run = !value;
 144
 145   state.reset();
 146   set_csr(CSR_MSTATUS, state.mstatus);
 147
 148   if (ext)
 149     ext->reset(); // reset the extension
 150 }
 151
 152 void processor_t::raise_interrupt(reg_t which)
 153 {
 154   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 155 }
 156
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt()
 167 {
 168   check_timer();
 169
 170   reg_t pending_interrupts = state.mip & state.mie;
 171
 172   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 173   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 174   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 175
 176   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 177   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 178   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 179
 180   if (enabled_interrupts)
 181     raise_interrupt(ctz(enabled_interrupts));
 182 }
 183
 184 void processor_t::check_timer()
 185 {
 186   if (sim->rtc >= state.mtimecmp)
 187     state.mip |= MIP_MTIP;
 188 }
 189
 190 static bool validate_priv(reg_t priv)
 191 {
 192   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 193 }
 194
 195 void processor_t::set_privilege(reg_t prv)
 196 {
 197   assert(validate_priv(prv));
 198   mmu->flush_tlb();
 199   state.prv = prv;
 200 }
 201
 202 void processor_t::take_trap(trap_t& t, reg_t epc)
 203 {
 204   if (debug)
 205     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 206             id, t.name(), epc);
 207
 208   // by default, trap to M-mode, unless delegated to S-mode
 209   reg_t bit = t.cause();
 210   reg_t deleg = state.medeleg;
 211   if (bit & ((reg_t)1 << (max_xlen-1)))
 212     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 213   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 214     // handle the trap in S-mode
 215     state.pc = state.stvec;
 216     state.scause = t.cause();
 217     state.sepc = epc;
 218     if (t.has_badaddr())
 219       state.sbadaddr = t.get_badaddr();
 220
 221     reg_t s = state.mstatus;
 222     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 223     s = set_field(s, MSTATUS_SPP, state.prv);
 224     s = set_field(s, MSTATUS_SIE, 0);
 225     set_csr(CSR_MSTATUS, s);
 226     set_privilege(PRV_S);
 227   } else {
 228     state.pc = DEFAULT_MTVEC;
 229     state.mcause = t.cause();
 230     state.mepc = epc;
 231     if (t.has_badaddr())
 232       state.mbadaddr = t.get_badaddr();
 233
 234     reg_t s = state.mstatus;
 235     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 236     s = set_field(s, MSTATUS_MPP, state.prv);
 237     s = set_field(s, MSTATUS_MIE, 0);
 238     set_csr(CSR_MSTATUS, s);
 239     set_privilege(PRV_M);
 240   }
 241
 242   yield_load_reservation();
 243 }
 244
 245 void processor_t::disasm(insn_t insn)
 246 {
 247   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 248   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 249           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 250 }
 251
 252 static bool validate_vm(int max_xlen, reg_t vm)
 253 {
 254   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 255     return true;
 256   if (max_xlen == 32 && vm == VM_SV32)
 257     return true;
 258   return vm == VM_MBARE;
 259 }
 260
 261 void processor_t::set_csr(int which, reg_t val)
 262 {
 263   val = zext_xlen(val);
 264   reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
 265   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 266   switch (which)
 267   {
 268     case CSR_FFLAGS:
 269       dirty_fp_state;
 270       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 271       break;
 272     case CSR_FRM:
 273       dirty_fp_state;
 274       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 275       break;
 276     case CSR_FCSR:
 277       dirty_fp_state;
 278       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 279       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 280       break;
 281     case CSR_MSTATUS: {
 282       if ((val ^ state.mstatus) &
 283           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 284         mmu->flush_tlb();
 285
 286       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 287                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 288                  | (ext ? MSTATUS_XS : 0);
 289
 290       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 291         mask |= MSTATUS_VM;
 292       if (validate_priv(get_field(val, MSTATUS_MPP)))
 293         mask |= MSTATUS_MPP;
 294
 295       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 296
 297       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 298       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 299       if (max_xlen == 32)
 300         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 301       else
 302         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 303
 304       // spike supports the notion of xlen < max_xlen, but current priv spec
 305       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 306       xlen = max_xlen;
 307       break;
 308     }
 309     case CSR_MIP: {
 310       reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
 311       state.mip = (state.mip & ~mask) | (val & mask);
 312       break;
 313     }
 314     case CSR_MIPI:
 315       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 316       break;
 317     case CSR_MIE:
 318       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 319       break;
 320     case CSR_MIDELEG:
 321       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 322       break;
 323     case CSR_MEDELEG: {
 324       reg_t mask = 0;
 325 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 326 #include "encoding.h"
 327 #undef DECLARE_CAUSE
 328       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 329       break;
 330     }
 331     case CSR_MUCOUNTEREN:
 332       state.mucounteren = val & 7;
 333       break;
 334     case CSR_MSCOUNTEREN:
 335       state.mscounteren = val & 7;
 336       break;
 337     case CSR_SSTATUS: {
 338       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 339                  | SSTATUS_XS | SSTATUS_PUM;
 340       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 341     }
 342     case CSR_SIP:
 343       return set_csr(CSR_MIP,
 344                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 345     case CSR_SIE:
 346       return set_csr(CSR_MIE,
 347                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 348     case CSR_SEPC: state.sepc = val; break;
 349     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 350     case CSR_SPTBR: state.sptbr = val; break;
 351     case CSR_SSCRATCH: state.sscratch = val; break;
 352     case CSR_SCAUSE: state.scause = val; break;
 353     case CSR_SBADADDR: state.sbadaddr = val; break;
 354     case CSR_MEPC: state.mepc = val; break;
 355     case CSR_MSCRATCH: state.mscratch = val; break;
 356     case CSR_MCAUSE: state.mcause = val; break;
 357     case CSR_MBADADDR: state.mbadaddr = val; break;
 358     case CSR_MTIMECMP:
 359       state.mip &= ~MIP_MTIP;
 360       state.mtimecmp = val;
 361       break;
 362     case CSR_MTOHOST:
 363       if (state.tohost == 0)
 364         state.tohost = val;
 365       break;
 366     case CSR_MFROMHOST:
 367       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 368       state.fromhost = val;
 369       break;
 370   }
 371 }
 372
 373 reg_t processor_t::get_csr(int which)
 374 {
 375   switch (which)
 376   {
 377     case CSR_FFLAGS:
 378       require_fp;
 379       if (!supports_extension('F'))
 380         break;
 381       return state.fflags;
 382     case CSR_FRM:
 383       require_fp;
 384       if (!supports_extension('F'))
 385         break;
 386       return state.frm;
 387     case CSR_FCSR:
 388       require_fp;
 389       if (!supports_extension('F'))
 390         break;
 391       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 392     case CSR_TIME:
 393     case CSR_INSTRET:
 394     case CSR_CYCLE:
 395       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 396         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 397       break;
 398     case CSR_STIME:
 399     case CSR_SINSTRET:
 400     case CSR_SCYCLE:
 401       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 402         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 403       break;
 404     case CSR_MUCOUNTEREN: return state.mucounteren;
 405     case CSR_MSCOUNTEREN: return state.mscounteren;
 406     case CSR_MUCYCLE_DELTA: return 0;
 407     case CSR_MUTIME_DELTA: return 0;
 408     case CSR_MUINSTRET_DELTA: return 0;
 409     case CSR_MSCYCLE_DELTA: return 0;
 410     case CSR_MSTIME_DELTA: return 0;
 411     case CSR_MSINSTRET_DELTA: return 0;
 412     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 413     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 414     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 415     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 416     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 417     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 418     case CSR_MTIME: return sim->rtc;
 419     case CSR_MCYCLE: return state.minstret;
 420     case CSR_MINSTRET: return state.minstret;
 421     case CSR_MTIMEH: if (xlen > 32) break; else return sim->rtc >> 32;
 422     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 423     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 424     case CSR_SSTATUS: {
 425       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 426                  | SSTATUS_XS | SSTATUS_PUM;
 427       reg_t sstatus = state.mstatus & mask;
 428       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 429           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 430         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 431       return sstatus;
 432     }
 433     case CSR_SIP: return state.mip & state.mideleg;
 434     case CSR_SIE: return state.mie & state.mideleg;
 435     case CSR_SEPC: return state.sepc;
 436     case CSR_SBADADDR: return state.sbadaddr;
 437     case CSR_STVEC: return state.stvec;
 438     case CSR_SCAUSE:
 439       if (max_xlen > xlen)
 440         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 441       return state.scause;
 442     case CSR_SPTBR: return state.sptbr;
 443     case CSR_SASID: return 0;
 444     case CSR_SSCRATCH: return state.sscratch;
 445     case CSR_MSTATUS: return state.mstatus;
 446     case CSR_MIP: return state.mip;
 447     case CSR_MIPI: return 0;
 448     case CSR_MIE: return state.mie;
 449     case CSR_MEPC: return state.mepc;
 450     case CSR_MSCRATCH: return state.mscratch;
 451     case CSR_MCAUSE: return state.mcause;
 452     case CSR_MBADADDR: return state.mbadaddr;
 453     case CSR_MTIMECMP: return state.mtimecmp;
 454     case CSR_MISA: return isa;
 455     case CSR_MARCHID: return 0;
 456     case CSR_MIMPID: return 0;
 457     case CSR_MVENDORID: return 0;
 458     case CSR_MHARTID: return id;
 459     case CSR_MTVEC: return DEFAULT_MTVEC;
 460     case CSR_MEDELEG: return state.medeleg;
 461     case CSR_MIDELEG: return state.mideleg;
 462     case CSR_MTOHOST:
 463       sim->get_htif()->tick(); // not necessary, but faster
 464       return state.tohost;
 465     case CSR_MFROMHOST:
 466       sim->get_htif()->tick(); // not necessary, but faster
 467       return state.fromhost;
 468     case CSR_MCFGADDR: return sim->memsz;
 469     case CSR_UARCH0:
 470     case CSR_UARCH1:
 471     case CSR_UARCH2:
 472     case CSR_UARCH3:
 473     case CSR_UARCH4:
 474     case CSR_UARCH5:
 475     case CSR_UARCH6:
 476     case CSR_UARCH7:
 477     case CSR_UARCH8:
 478     case CSR_UARCH9:
 479     case CSR_UARCH10:
 480     case CSR_UARCH11:
 481     case CSR_UARCH12:
 482     case CSR_UARCH13:
 483     case CSR_UARCH14:
 484     case CSR_UARCH15:
 485       return 0;
 486   }
 487   throw trap_illegal_instruction();
 488 }
 489
 490 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 491 {
 492   throw trap_illegal_instruction();
 493 }
 494
 495 insn_func_t processor_t::decode_insn(insn_t insn)
 496 {
 497   // look up opcode in hash table
 498   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 499   insn_desc_t desc = opcode_cache[idx];
 500
 501   if (unlikely(insn.bits() != desc.match)) {
 502     // fall back to linear search
 503     insn_desc_t* p = &instructions[0];
 504     while ((insn.bits() & p->mask) != p->match)
 505       p++;
 506     desc = *p;
 507
 508     if (p->mask != 0 && p > &instructions[0]) {
 509       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 510         // move to front of opcode list to reduce miss penalty
 511         while (--p >= &instructions[0])
 512           *(p+1) = *p;
 513         instructions[0] = desc;
 514       }
 515     }
 516
 517     opcode_cache[idx] = desc;
 518     opcode_cache[idx].match = insn.bits();
 519   }
 520
 521   return xlen == 64 ? desc.rv64 : desc.rv32;
 522 }
 523
 524 void processor_t::register_insn(insn_desc_t desc)
 525 {
 526   instructions.push_back(desc);
 527 }
 528
 529 void processor_t::build_opcode_map()
 530 {
 531   struct cmp {
 532     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 533       if (lhs.match == rhs.match)
 534         return lhs.mask > rhs.mask;
 535       return lhs.match > rhs.match;
 536     }
 537   };
 538   std::sort(instructions.begin(), instructions.end(), cmp());
 539
 540   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 541     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 542 }
 543
 544 void processor_t::register_extension(extension_t* x)
 545 {
 546   for (auto insn : x->get_instructions())
 547     register_insn(insn);
 548   build_opcode_map();
 549   for (auto disasm_insn : x->get_disasms())
 550     disassembler->add_insn(disasm_insn);
 551   if (ext != NULL)
 552     throw std::logic_error("only one extension may be registered");
 553   ext = x;
 554   x->set_processor(this);
 555 }
 556
 557 void processor_t::register_base_instructions()
 558 {
 559   #define DECLARE_INSN(name, match, mask) \
 560     insn_bits_t name##_match = (match), name##_mask = (mask);
 561   #include "encoding.h"
 562   #undef DECLARE_INSN
 563
 564   #define DEFINE_INSN(name) \
 565     REGISTER_INSN(this, name, name##_match, name##_mask)
 566   #include "insn_list.h"
 567   #undef DEFINE_INSN
 568
 569   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 570   build_opcode_map();
 571 }
 572
 573 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 574 {
 575   try {
 576     auto res = get_csr(addr / (max_xlen / 8));
 577     memcpy(bytes, &res, len);
 578     return true;
 579   } catch (trap_illegal_instruction& t) {
 580     return false;
 581   }
 582 }
 583
 584 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 585 {
 586   try {
 587     reg_t value = 0;
 588     memcpy(&value, bytes, len);
 589     set_csr(addr / (max_xlen / 8), value);
 590     return true;
 591   } catch (trap_illegal_instruction& t) {
 592     return false;
 593   }
 594 }