riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  25 {
  26   parse_isa_string(isa);
  27   register_base_instructions();
  28
  29   mmu = new mmu_t(sim, this);
  30   disassembler = new disassembler_t(max_xlen);
  31
  32   reset();
  33 }
  34
  35 processor_t::~processor_t()
  36 {
  37 #ifdef RISCV_ENABLE_HISTOGRAM
  38   if (histogram_enabled)
  39   {
  40     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  41     for (auto it : pc_histogram)
  42       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  43   }
  44 #endif
  45
  46   delete mmu;
  47   delete disassembler;
  48 }
  49
  50 static void bad_isa_string(const char* isa)
  51 {
  52   fprintf(stderr, "error: bad --isa option %s\n", isa);
  53   abort();
  54 }
  55
  56 void processor_t::parse_isa_string(const char* str)
  57 {
  58   std::string lowercase, tmp;
  59   for (const char *r = str; *r; r++)
  60     lowercase += std::tolower(*r);
  61
  62   const char* p = lowercase.c_str();
  63   const char* all_subsets = "imafdc";
  64
  65   max_xlen = 64;
  66   isa = reg_t(2) << 62;
  67
  68   if (strncmp(p, "rv32", 4) == 0)
  69     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  70   else if (strncmp(p, "rv64", 4) == 0)
  71     p += 4;
  72   else if (strncmp(p, "rv", 2) == 0)
  73     p += 2;
  74
  75   if (!*p) {
  76     p = all_subsets;
  77   } else if (*p == 'g') { // treat "G" as "IMAFD"
  78     tmp = std::string("imafd") + (p+1);
  79     p = &tmp[0];
  80   } else if (*p != 'i') {
  81     bad_isa_string(str);
  82   }
  83
  84   isa_string = "rv" + std::to_string(max_xlen) + p;
  85   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  86   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111
 112   max_isa = isa;
 113 }
 114
 115 void state_t::reset()
 116 {
 117   memset(this, 0, sizeof(*this));
 118   prv = PRV_M;
 119   pc = DEFAULT_RSTVEC;
 120   mtvec = DEFAULT_MTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 void processor_t::raise_interrupt(reg_t which)
 157 {
 158   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 159 }
 160
 161 // Count number of contiguous 0 bits starting from the LSB.
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt()
 172 {
 173   reg_t pending_interrupts = state.mip & state.mie;
 174
 175   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 176   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 177   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 178
 179   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 180   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 181   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (enabled_interrupts)
 184     raise_interrupt(ctz(enabled_interrupts));
 185 }
 186
 187 void processor_t::set_privilege(reg_t prv)
 188 {
 189   assert(prv <= PRV_M);
 190   if (prv == PRV_H)
 191     prv = PRV_U;
 192   mmu->flush_tlb();
 193   state.prv = prv;
 194 }
 195
 196 void processor_t::enter_debug_mode(uint8_t cause)
 197 {
 198   state.dcsr.cause = cause;
 199   state.dcsr.prv = state.prv;
 200   set_privilege(PRV_M);
 201   state.dpc = state.pc;
 202   state.pc = DEBUG_ROM_START;
 203 }
 204
 205 void processor_t::take_trap(trap_t& t, reg_t epc)
 206 {
 207   if (debug) {
 208     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 209             id, t.name(), epc);
 210     if (t.has_badaddr())
 211       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 212           t.get_badaddr());
 213   }
 214
 215   if (t.cause() == CAUSE_BREAKPOINT && (
 216               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 217               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 218               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 219               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 220     enter_debug_mode(DCSR_CAUSE_SWBP);
 221     return;
 222   }
 223
 224   if (state.dcsr.cause) {
 225     state.pc = DEBUG_ROM_EXCEPTION;
 226     return;
 227   }
 228
 229   // by default, trap to M-mode, unless delegated to S-mode
 230   reg_t bit = t.cause();
 231   reg_t deleg = state.medeleg;
 232   if (bit & ((reg_t)1 << (max_xlen-1)))
 233     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 234   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 235     // handle the trap in S-mode
 236     state.pc = state.stvec;
 237     state.scause = t.cause();
 238     state.sepc = epc;
 239     if (t.has_badaddr())
 240       state.sbadaddr = t.get_badaddr();
 241
 242     reg_t s = state.mstatus;
 243     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 244     s = set_field(s, MSTATUS_SPP, state.prv);
 245     s = set_field(s, MSTATUS_SIE, 0);
 246     set_csr(CSR_MSTATUS, s);
 247     set_privilege(PRV_S);
 248   } else {
 249     state.pc = state.mtvec;
 250     state.mepc = epc;
 251     state.mcause = t.cause();
 252     if (t.has_badaddr())
 253       state.mbadaddr = t.get_badaddr();
 254
 255     reg_t s = state.mstatus;
 256     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 257     s = set_field(s, MSTATUS_MPP, state.prv);
 258     s = set_field(s, MSTATUS_MIE, 0);
 259     set_csr(CSR_MSTATUS, s);
 260     set_privilege(PRV_M);
 261   }
 262
 263   yield_load_reservation();
 264 }
 265
 266 void processor_t::disasm(insn_t insn)
 267 {
 268   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 269   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 270           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 271 }
 272
 273 static bool validate_vm(int max_xlen, reg_t vm)
 274 {
 275   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 276     return true;
 277   if (max_xlen == 32 && vm == VM_SV32)
 278     return true;
 279   return vm == VM_MBARE;
 280 }
 281
 282 int processor_t::paddr_bits()
 283 {
 284   assert(xlen == max_xlen);
 285   return max_xlen == 64 ? 50 : 34;
 286 }
 287
 288 void processor_t::set_csr(int which, reg_t val)
 289 {
 290   val = zext_xlen(val);
 291   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 292   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 293   switch (which)
 294   {
 295     case CSR_FFLAGS:
 296       dirty_fp_state;
 297       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 298       break;
 299     case CSR_FRM:
 300       dirty_fp_state;
 301       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 302       break;
 303     case CSR_FCSR:
 304       dirty_fp_state;
 305       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 306       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 307       break;
 308     case CSR_MSTATUS: {
 309       if ((val ^ state.mstatus) &
 310           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 311         mmu->flush_tlb();
 312
 313       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 314                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 315                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 316
 317       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 318         mask |= MSTATUS_VM;
 319
 320       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 321
 322       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 323       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 324       if (max_xlen == 32)
 325         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 326       else
 327         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 328
 329       // spike supports the notion of xlen < max_xlen, but current priv spec
 330       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 331       xlen = max_xlen;
 332       break;
 333     }
 334     case CSR_MIP: {
 335       reg_t mask = MIP_SSIP | MIP_STIP;
 336       state.mip = (state.mip & ~mask) | (val & mask);
 337       break;
 338     }
 339     case CSR_MIE:
 340       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 341       break;
 342     case CSR_MIDELEG:
 343       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 344       break;
 345     case CSR_MEDELEG: {
 346       reg_t mask = 0;
 347 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 348 #include "encoding.h"
 349 #undef DECLARE_CAUSE
 350       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 351       break;
 352     }
 353     case CSR_MINSTRET:
 354     case CSR_MCYCLE:
 355       if (xlen == 32)
 356         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 357       else
 358         state.minstret = val;
 359       break;
 360     case CSR_MINSTRETH:
 361     case CSR_MCYCLEH:
 362       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 363       break;
 364     case CSR_MUCOUNTEREN:
 365       state.mucounteren = val;
 366       break;
 367     case CSR_MSCOUNTEREN:
 368       state.mscounteren = val;
 369       break;
 370     case CSR_SSTATUS: {
 371       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 372                  | SSTATUS_XS | SSTATUS_PUM;
 373       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 374     }
 375     case CSR_SIP: {
 376       reg_t mask = MIP_SSIP & state.mideleg;
 377       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 378     }
 379     case CSR_SIE:
 380       return set_csr(CSR_MIE,
 381                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 382     case CSR_SPTBR: {
 383       // upper bits of sptbr are the ASID; we only support ASID = 0
 384       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 385       break;
 386     }
 387     case CSR_SEPC: state.sepc = val; break;
 388     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 389     case CSR_SSCRATCH: state.sscratch = val; break;
 390     case CSR_SCAUSE: state.scause = val; break;
 391     case CSR_SBADADDR: state.sbadaddr = val; break;
 392     case CSR_MEPC: state.mepc = val; break;
 393     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 394     case CSR_MSCRATCH: state.mscratch = val; break;
 395     case CSR_MCAUSE: state.mcause = val; break;
 396     case CSR_MBADADDR: state.mbadaddr = val; break;
 397     case CSR_MISA: {
 398       if (!(val & (1L << ('F' - 'A'))))
 399         val &= ~(1L << ('D' - 'A'));
 400
 401       // allow MAFDC bits in MISA to be modified
 402       reg_t mask = 0;
 403       mask |= 1L << ('M' - 'A');
 404       mask |= 1L << ('A' - 'A');
 405       mask |= 1L << ('F' - 'A');
 406       mask |= 1L << ('D' - 'A');
 407       mask |= 1L << ('C' - 'A');
 408       mask &= max_isa;
 409
 410       isa = (val & mask) | (isa & ~mask);
 411       break;
 412     }
 413     case CSR_TSELECT:
 414       if (val < state.num_triggers) {
 415         state.tselect = val;
 416       }
 417       break;
 418     case CSR_TDATA1:
 419       {
 420         mcontrol_t *mc = &state.mcontrol[state.tselect];
 421         if (mc->dmode && !state.dcsr.cause) {
 422           break;
 423         }
 424         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 425         mc->select = get_field(val, MCONTROL_SELECT);
 426         mc->timing = get_field(val, MCONTROL_TIMING);
 427         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 428         mc->chain = get_field(val, MCONTROL_CHAIN);
 429         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 430         mc->m = get_field(val, MCONTROL_M);
 431         mc->h = get_field(val, MCONTROL_H);
 432         mc->s = get_field(val, MCONTROL_S);
 433         mc->u = get_field(val, MCONTROL_U);
 434         mc->execute = get_field(val, MCONTROL_EXECUTE);
 435         mc->store = get_field(val, MCONTROL_STORE);
 436         mc->load = get_field(val, MCONTROL_LOAD);
 437         // Assume we're here because of csrw.
 438         if (mc->execute)
 439           mc->timing = 0;
 440         trigger_updated();
 441       }
 442       break;
 443     case CSR_TDATA2:
 444       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 445         break;
 446       }
 447       if (state.tselect < state.num_triggers) {
 448         state.tdata2[state.tselect] = val;
 449       }
 450       break;
 451     case CSR_DCSR:
 452       state.dcsr.prv = get_field(val, DCSR_PRV);
 453       state.dcsr.step = get_field(val, DCSR_STEP);
 454       // TODO: ndreset and fullreset
 455       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 456       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 457       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 458       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 459       state.dcsr.halt = get_field(val, DCSR_HALT);
 460       break;
 461     case CSR_DPC:
 462       state.dpc = val;
 463       break;
 464     case CSR_DSCRATCH:
 465       state.dscratch = val;
 466       break;
 467   }
 468 }
 469
 470 reg_t processor_t::get_csr(int which)
 471 {
 472   reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
 473                  state.prv == PRV_S ? state.mscounteren : -1U;
 474   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 475
 476   if (ctr_ok) {
 477     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 478       return 0;
 479     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 480       return 0;
 481   }
 482   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 483     return 0;
 484   if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 485     return 0;
 486   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 487     return 0;
 488
 489   switch (which)
 490   {
 491     case CSR_FFLAGS:
 492       require_fp;
 493       if (!supports_extension('F'))
 494         break;
 495       return state.fflags;
 496     case CSR_FRM:
 497       require_fp;
 498       if (!supports_extension('F'))
 499         break;
 500       return state.frm;
 501     case CSR_FCSR:
 502       require_fp;
 503       if (!supports_extension('F'))
 504         break;
 505       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 506     case CSR_INSTRET:
 507     case CSR_CYCLE:
 508       if (ctr_ok)
 509         return state.minstret;
 510       break;
 511     case CSR_MINSTRET:
 512     case CSR_MCYCLE:
 513       return state.minstret;
 514     case CSR_MINSTRETH:
 515     case CSR_MCYCLEH:
 516       if (xlen == 32)
 517         return state.minstret >> 32;
 518       break;
 519     case CSR_MUCOUNTEREN: return state.mucounteren;
 520     case CSR_MSCOUNTEREN: return state.mscounteren;
 521     case CSR_SSTATUS: {
 522       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 523                  | SSTATUS_XS | SSTATUS_PUM;
 524       reg_t sstatus = state.mstatus & mask;
 525       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 526           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 527         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 528       return sstatus;
 529     }
 530     case CSR_SIP: return state.mip & state.mideleg;
 531     case CSR_SIE: return state.mie & state.mideleg;
 532     case CSR_SEPC: return state.sepc;
 533     case CSR_SBADADDR: return state.sbadaddr;
 534     case CSR_STVEC: return state.stvec;
 535     case CSR_SCAUSE:
 536       if (max_xlen > xlen)
 537         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 538       return state.scause;
 539     case CSR_SPTBR: return state.sptbr;
 540     case CSR_SSCRATCH: return state.sscratch;
 541     case CSR_MSTATUS: return state.mstatus;
 542     case CSR_MIP: return state.mip;
 543     case CSR_MIE: return state.mie;
 544     case CSR_MEPC: return state.mepc;
 545     case CSR_MSCRATCH: return state.mscratch;
 546     case CSR_MCAUSE: return state.mcause;
 547     case CSR_MBADADDR: return state.mbadaddr;
 548     case CSR_MISA: return isa;
 549     case CSR_MARCHID: return 0;
 550     case CSR_MIMPID: return 0;
 551     case CSR_MVENDORID: return 0;
 552     case CSR_MHARTID: return id;
 553     case CSR_MTVEC: return state.mtvec;
 554     case CSR_MEDELEG: return state.medeleg;
 555     case CSR_MIDELEG: return state.mideleg;
 556     case CSR_TSELECT: return state.tselect;
 557     case CSR_TDATA1:
 558       if (state.tselect < state.num_triggers) {
 559         reg_t v = 0;
 560         mcontrol_t *mc = &state.mcontrol[state.tselect];
 561         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 562         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 563         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 564         v = set_field(v, MCONTROL_SELECT, mc->select);
 565         v = set_field(v, MCONTROL_TIMING, mc->timing);
 566         v = set_field(v, MCONTROL_ACTION, mc->action);
 567         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 568         v = set_field(v, MCONTROL_MATCH, mc->match);
 569         v = set_field(v, MCONTROL_M, mc->m);
 570         v = set_field(v, MCONTROL_H, mc->h);
 571         v = set_field(v, MCONTROL_S, mc->s);
 572         v = set_field(v, MCONTROL_U, mc->u);
 573         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 574         v = set_field(v, MCONTROL_STORE, mc->store);
 575         v = set_field(v, MCONTROL_LOAD, mc->load);
 576         return v;
 577       } else {
 578         return 0;
 579       }
 580       break;
 581     case CSR_TDATA2:
 582       if (state.tselect < state.num_triggers) {
 583         return state.tdata2[state.tselect];
 584       } else {
 585         return 0;
 586       }
 587       break;
 588     case CSR_TDATA3: return 0;
 589     case CSR_DCSR:
 590       {
 591         uint32_t v = 0;
 592         v = set_field(v, DCSR_XDEBUGVER, 1);
 593         v = set_field(v, DCSR_NDRESET, 0);
 594         v = set_field(v, DCSR_FULLRESET, 0);
 595         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 596         v = set_field(v, DCSR_STEP, state.dcsr.step);
 597         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 598         v = set_field(v, DCSR_STOPCYCLE, 0);
 599         v = set_field(v, DCSR_STOPTIME, 0);
 600         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 601         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 602         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 603         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 604         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 605         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 606         return v;
 607       }
 608     case CSR_DPC:
 609       return state.dpc;
 610     case CSR_DSCRATCH:
 611       return state.dscratch;
 612   }
 613   throw trap_illegal_instruction();
 614 }
 615
 616 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 617 {
 618   throw trap_illegal_instruction();
 619 }
 620
 621 insn_func_t processor_t::decode_insn(insn_t insn)
 622 {
 623   // look up opcode in hash table
 624   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 625   insn_desc_t desc = opcode_cache[idx];
 626
 627   if (unlikely(insn.bits() != desc.match)) {
 628     // fall back to linear search
 629     insn_desc_t* p = &instructions[0];
 630     while ((insn.bits() & p->mask) != p->match)
 631       p++;
 632     desc = *p;
 633
 634     if (p->mask != 0 && p > &instructions[0]) {
 635       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 636         // move to front of opcode list to reduce miss penalty
 637         while (--p >= &instructions[0])
 638           *(p+1) = *p;
 639         instructions[0] = desc;
 640       }
 641     }
 642
 643     opcode_cache[idx] = desc;
 644     opcode_cache[idx].match = insn.bits();
 645   }
 646
 647   return xlen == 64 ? desc.rv64 : desc.rv32;
 648 }
 649
 650 void processor_t::register_insn(insn_desc_t desc)
 651 {
 652   instructions.push_back(desc);
 653 }
 654
 655 void processor_t::build_opcode_map()
 656 {
 657   struct cmp {
 658     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 659       if (lhs.match == rhs.match)
 660         return lhs.mask > rhs.mask;
 661       return lhs.match > rhs.match;
 662     }
 663   };
 664   std::sort(instructions.begin(), instructions.end(), cmp());
 665
 666   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 667     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 668 }
 669
 670 void processor_t::register_extension(extension_t* x)
 671 {
 672   for (auto insn : x->get_instructions())
 673     register_insn(insn);
 674   build_opcode_map();
 675   for (auto disasm_insn : x->get_disasms())
 676     disassembler->add_insn(disasm_insn);
 677   if (ext != NULL)
 678     throw std::logic_error("only one extension may be registered");
 679   ext = x;
 680   x->set_processor(this);
 681 }
 682
 683 void processor_t::register_base_instructions()
 684 {
 685   #define DECLARE_INSN(name, match, mask) \
 686     insn_bits_t name##_match = (match), name##_mask = (mask);
 687   #include "encoding.h"
 688   #undef DECLARE_INSN
 689
 690   #define DEFINE_INSN(name) \
 691     REGISTER_INSN(this, name, name##_match, name##_mask)
 692   #include "insn_list.h"
 693   #undef DEFINE_INSN
 694
 695   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 696   build_opcode_map();
 697 }
 698
 699 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 700 {
 701   return false;
 702 }
 703
 704 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 705 {
 706   switch (addr)
 707   {
 708     case 0:
 709       state.mip &= ~MIP_MSIP;
 710       if (bytes[0] & 1)
 711         state.mip |= MIP_MSIP;
 712       return true;
 713
 714     default:
 715       return false;
 716   }
 717 }
 718
 719 void processor_t::trigger_updated()
 720 {
 721   mmu->flush_tlb();
 722   mmu->check_triggers_fetch = false;
 723   mmu->check_triggers_load = false;
 724   mmu->check_triggers_store = false;
 725
 726   for (unsigned i = 0; i < state.num_triggers; i++) {
 727     if (state.mcontrol[i].execute) {
 728       mmu->check_triggers_fetch = true;
 729     }
 730     if (state.mcontrol[i].load) {
 731       mmu->check_triggers_load = true;
 732     }
 733     if (state.mcontrol[i].store) {
 734       mmu->check_triggers_store = true;
 735     }
 736   }
 737 }