1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
)
23 : sim(sim
), ext(NULL
), disassembler(new disassembler_t
),
24 id(id
), run(false), debug(false)
26 parse_isa_string(isa
);
28 mmu
= new mmu_t(sim
->mem
, sim
->memsz
);
29 mmu
->set_processor(this);
33 register_base_instructions();
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= 0, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
89 isa
|= 1L << (*p
- 'a');
91 if (auto next
= strchr(all_subsets
, *p
)) {
92 all_subsets
= next
+ 1;
94 } else if (*p
== 'x') {
95 const char* ext
= p
+1, *end
= ext
;
98 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
105 if (supports_extension('D') && !supports_extension('F'))
108 // if we have IMAFD, advertise G, too
109 if (supports_extension('I') && supports_extension('M') &&
110 supports_extension('A') && supports_extension('D'))
111 isa
|= 1L << ('g' - 'a');
113 // advertise support for supervisor and user modes
114 isa
|= 1L << ('s' - 'a');
115 isa
|= 1L << ('u' - 'a');
118 void state_t::reset()
120 memset(this, 0, sizeof(*this));
123 load_reservation
= -1;
126 void processor_t::set_debug(bool value
)
130 ext
->set_debug(value
);
133 void processor_t::set_histogram(bool value
)
135 histogram_enabled
= value
;
136 #ifndef RISCV_ENABLE_HISTOGRAM
138 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
139 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
144 void processor_t::reset(bool value
)
151 set_csr(CSR_MSTATUS
, state
.mstatus
);
154 ext
->reset(); // reset the extension
157 void processor_t::raise_interrupt(reg_t which
)
159 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
162 static int ctz(reg_t val
)
166 while ((val
& 1) == 0)
171 void processor_t::take_interrupt()
175 reg_t interrupts
= state
.mip
& state
.mie
;
177 reg_t m_interrupts
= interrupts
& ~state
.mideleg
;
178 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
179 if ((state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
)) && m_interrupts
)
180 raise_interrupt(ctz(m_interrupts
));
182 reg_t s_interrupts
= interrupts
& state
.mideleg
;
183 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
184 if ((state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
)) && s_interrupts
)
185 raise_interrupt(ctz(s_interrupts
));
188 void processor_t::check_timer()
190 if (sim
->rtc
>= state
.mtimecmp
)
191 state
.mip
|= MIP_MTIP
;
194 static bool validate_priv(reg_t priv
)
196 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
199 void processor_t::set_privilege(reg_t prv
)
201 assert(validate_priv(prv
));
206 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
209 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
212 // by default, trap to M-mode, unless delegated to S-mode
213 reg_t bit
= t
.cause();
214 reg_t deleg
= state
.medeleg
;
215 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
216 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
217 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
218 // handle the trap in S-mode
219 state
.pc
= state
.stvec
;
220 state
.scause
= t
.cause();
223 state
.sbadaddr
= t
.get_badaddr();
225 reg_t s
= state
.mstatus
;
226 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
227 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
228 s
= set_field(s
, MSTATUS_SIE
, 0);
229 set_csr(CSR_MSTATUS
, s
);
230 set_privilege(PRV_S
);
232 state
.pc
= DEFAULT_MTVEC
;
233 state
.mcause
= t
.cause();
236 state
.mbadaddr
= t
.get_badaddr();
238 reg_t s
= state
.mstatus
;
239 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
240 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
241 s
= set_field(s
, MSTATUS_MIE
, 0);
242 set_csr(CSR_MSTATUS
, s
);
243 set_privilege(PRV_M
);
246 yield_load_reservation();
249 void processor_t::disasm(insn_t insn
)
251 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
252 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
253 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
256 static bool validate_vm(int max_xlen
, reg_t vm
)
258 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
260 if (max_xlen
== 32 && vm
== VM_SV32
)
262 return vm
== VM_MBARE
;
265 void processor_t::set_csr(int which
, reg_t val
)
267 val
= zext_xlen(val
);
268 reg_t all_ints
= MIP_SSIP
| MIP_MSIP
| MIP_STIP
| MIP_MTIP
| (1UL << IRQ_HOST
);
269 reg_t s_ints
= MIP_SSIP
| MIP_STIP
;
274 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
278 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
282 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
283 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
287 // this implementation ignores writes to MTIME
291 // this implementation ignores writes to MTIME
296 state
.sutime_delta
= val
| (state
.sutime_delta
>> 32 << 32);
298 state
.sutime_delta
= val
;
301 val
= ((val
<< 32) - sim
->rtc
) >> 32;
302 state
.sutime_delta
= (val
<< 32) | (uint32_t)state
.sutime_delta
;
306 val
-= state
.minstret
;
308 state
.suinstret_delta
= val
| (state
.suinstret_delta
>> 32 << 32);
310 state
.suinstret_delta
= val
;
314 val
= ((val
<< 32) - state
.minstret
) >> 32;
315 state
.suinstret_delta
= (val
<< 32) | (uint32_t)state
.suinstret_delta
;
318 if ((val
^ state
.mstatus
) &
319 (MSTATUS_VM
| MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
))
322 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
323 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
324 | (ext
? MSTATUS_XS
: 0);
326 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
328 if (validate_priv(get_field(val
, MSTATUS_MPP
)))
331 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
333 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
334 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
336 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
338 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
340 // spike supports the notion of xlen < max_xlen, but current priv spec
341 // doesn't provide a mechanism to run RV32 software on an RV64 machine
346 reg_t mask
= all_ints
&~ MIP_MTIP
;
347 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
351 state
.mip
= set_field(state
.mip
, MIP_MSIP
, val
& 1);
354 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
357 state
.mideleg
= (state
.mideleg
& ~s_ints
) | (val
& s_ints
);
361 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
362 #include "encoding.h"
364 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
368 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
369 | SSTATUS_XS
| SSTATUS_PUM
;
370 set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
374 reg_t mask
= s_ints
&~ MIP_STIP
;
375 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
380 state
.mie
= (state
.mie
& ~mask
) | (val
& mask
);
383 case CSR_SEPC
: state
.sepc
= val
; break;
384 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
385 case CSR_SPTBR
: state
.sptbr
= val
; break;
386 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
387 case CSR_SCAUSE
: state
.scause
= val
; break;
388 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
389 case CSR_MEPC
: state
.mepc
= val
; break;
390 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
391 case CSR_MCAUSE
: state
.mcause
= val
; break;
392 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
394 state
.mip
&= ~MIP_MTIP
;
395 state
.mtimecmp
= val
;
398 if (state
.tohost
== 0)
402 state
.mip
= (state
.mip
& ~(1 << IRQ_HOST
)) | (val
? (1 << IRQ_HOST
) : 0);
403 state
.fromhost
= val
;
408 reg_t
processor_t::get_csr(int which
)
414 if (!supports_extension('F'))
419 if (!supports_extension('F'))
424 if (!supports_extension('F'))
426 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
434 return sim
->rtc
>> 32;
437 return sim
->rtc
+ state
.sutime_delta
;
442 return state
.minstret
+ state
.suinstret_delta
;
447 return (sim
->rtc
+ state
.sutime_delta
) >> 32;
454 return (state
.minstret
+ state
.suinstret_delta
) >> 32;
456 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
457 | SSTATUS_XS
| SSTATUS_PUM
;
458 reg_t sstatus
= state
.mstatus
& mask
;
459 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
460 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
461 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
464 case CSR_SIP
: return state
.mip
& (MIP_SSIP
| MIP_STIP
);
465 case CSR_SIE
: return state
.mie
& (MIP_SSIP
| MIP_STIP
);
466 case CSR_SEPC
: return state
.sepc
;
467 case CSR_SBADADDR
: return state
.sbadaddr
;
468 case CSR_STVEC
: return state
.stvec
;
471 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
473 case CSR_SPTBR
: return state
.sptbr
;
474 case CSR_SASID
: return 0;
475 case CSR_SSCRATCH
: return state
.sscratch
;
476 case CSR_MSTATUS
: return state
.mstatus
;
477 case CSR_MIP
: return state
.mip
;
478 case CSR_MIPI
: return 0;
479 case CSR_MIE
: return state
.mie
;
480 case CSR_MEPC
: return state
.mepc
;
481 case CSR_MSCRATCH
: return state
.mscratch
;
482 case CSR_MCAUSE
: return state
.mcause
;
483 case CSR_MBADADDR
: return state
.mbadaddr
;
484 case CSR_MTIMECMP
: return state
.mtimecmp
;
485 case CSR_MISA
: return isa
;
486 case CSR_MARCHID
: return 0;
487 case CSR_MIMPID
: return 0;
488 case CSR_MVENDORID
: return 0;
489 case CSR_MHARTID
: return id
;
490 case CSR_MTVEC
: return DEFAULT_MTVEC
;
491 case CSR_MEDELEG
: return state
.medeleg
;
492 case CSR_MIDELEG
: return state
.mideleg
;
494 sim
->get_htif()->tick(); // not necessary, but faster
497 sim
->get_htif()->tick(); // not necessary, but faster
498 return state
.fromhost
;
499 case CSR_MCFGADDR
: return sim
->memsz
;
518 throw trap_illegal_instruction();
521 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
523 throw trap_illegal_instruction();
526 insn_func_t
processor_t::decode_insn(insn_t insn
)
528 // look up opcode in hash table
529 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
530 insn_desc_t desc
= opcode_cache
[idx
];
532 if (unlikely(insn
.bits() != desc
.match
)) {
533 // fall back to linear search
534 insn_desc_t
* p
= &instructions
[0];
535 while ((insn
.bits() & p
->mask
) != p
->match
)
539 if (p
->mask
!= 0 && p
> &instructions
[0]) {
540 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
541 // move to front of opcode list to reduce miss penalty
542 while (--p
>= &instructions
[0])
544 instructions
[0] = desc
;
548 opcode_cache
[idx
] = desc
;
549 opcode_cache
[idx
].match
= insn
.bits();
552 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
555 void processor_t::register_insn(insn_desc_t desc
)
557 instructions
.push_back(desc
);
560 void processor_t::build_opcode_map()
563 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
564 if (lhs
.match
== rhs
.match
)
565 return lhs
.mask
> rhs
.mask
;
566 return lhs
.match
> rhs
.match
;
569 std::sort(instructions
.begin(), instructions
.end(), cmp());
571 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
572 opcode_cache
[i
] = {1, 0, &illegal_instruction
, &illegal_instruction
};
575 void processor_t::register_extension(extension_t
* x
)
577 for (auto insn
: x
->get_instructions())
580 for (auto disasm_insn
: x
->get_disasms())
581 disassembler
->add_insn(disasm_insn
);
583 throw std::logic_error("only one extension may be registered");
585 x
->set_processor(this);
588 void processor_t::register_base_instructions()
590 #define DECLARE_INSN(name, match, mask) \
591 insn_bits_t name##_match = (match), name##_mask = (mask);
592 #include "encoding.h"
595 #define DEFINE_INSN(name) \
596 REGISTER_INSN(this, name, name##_match, name##_mask)
597 #include "insn_list.h"
600 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
604 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
607 auto res
= get_csr(addr
/ (max_xlen
/ 8));
608 memcpy(bytes
, &res
, len
);
610 } catch (trap_illegal_instruction
& t
) {
615 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
619 memcpy(&value
, bytes
, len
);
620 set_csr(addr
/ (max_xlen
/ 8), value
);
622 } catch (trap_illegal_instruction
& t
) {