riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include "gdbserver.h"
  12 #include <cinttypes>
  13 #include <cmath>
  14 #include <cstdlib>
  15 #include <iostream>
  16 #include <assert.h>
  17 #include <limits.h>
  18 #include <stdexcept>
  19 #include <algorithm>
  20
  21 #undef STATE
  22 #define STATE state
  23
  24 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  25         bool halt_on_reset)
  26   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
  27     id(id), run(false), halt_on_reset(halt_on_reset)
  28 {
  29   parse_isa_string(isa);
  30
  31   mmu = new mmu_t(sim, this);
  32
  33   reset(true);
  34
  35   register_base_instructions();
  36 }
  37
  38 processor_t::~processor_t()
  39 {
  40 #ifdef RISCV_ENABLE_HISTOGRAM
  41   if (histogram_enabled)
  42   {
  43     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  44     for (auto it : pc_histogram)
  45       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  46   }
  47 #endif
  48
  49   delete mmu;
  50   delete disassembler;
  51 }
  52
  53 static void bad_isa_string(const char* isa)
  54 {
  55   fprintf(stderr, "error: bad --isa option %s\n", isa);
  56   abort();
  57 }
  58
  59 void processor_t::parse_isa_string(const char* str)
  60 {
  61   std::string lowercase, tmp;
  62   for (const char *r = str; *r; r++)
  63     lowercase += std::tolower(*r);
  64
  65   const char* p = lowercase.c_str();
  66   const char* all_subsets = "imafdc";
  67
  68   max_xlen = 64;
  69   isa = reg_t(2) << 62;
  70
  71   if (strncmp(p, "rv32", 4) == 0)
  72     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  73   else if (strncmp(p, "rv64", 4) == 0)
  74     p += 4;
  75   else if (strncmp(p, "rv", 2) == 0)
  76     p += 2;
  77
  78   if (!*p) {
  79     p = all_subsets;
  80   } else if (*p == 'g') { // treat "G" as "IMAFD"
  81     tmp = std::string("imafd") + (p+1);
  82     p = &tmp[0];
  83   } else if (*p != 'i') {
  84     bad_isa_string(str);
  85   }
  86
  87   isa_string = "rv" + std::to_string(max_xlen) + p;
  88   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  89
  90   while (*p) {
  91     isa |= 1L << (*p - 'a');
  92
  93     if (auto next = strchr(all_subsets, *p)) {
  94       all_subsets = next + 1;
  95       p++;
  96     } else if (*p == 'x') {
  97       const char* ext = p+1, *end = ext;
  98       while (islower(*end))
  99         end++;
 100       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 101       p = end;
 102     } else {
 103       bad_isa_string(str);
 104     }
 105   }
 106
 107   if (supports_extension('D') && !supports_extension('F'))
 108     bad_isa_string(str);
 109
 110   // advertise support for supervisor and user modes
 111   isa |= 1L << ('s' - 'a');
 112   isa |= 1L << ('u' - 'a');
 113 }
 114
 115 void state_t::reset()
 116 {
 117   memset(this, 0, sizeof(*this));
 118   prv = PRV_M;
 119   pc = DEFAULT_RSTVEC;
 120   mtvec = DEFAULT_MTVEC;
 121   load_reservation = -1;
 122 }
 123
 124 void processor_t::set_debug(bool value)
 125 {
 126   debug = value;
 127   if (ext)
 128     ext->set_debug(value);
 129 }
 130
 131 void processor_t::set_histogram(bool value)
 132 {
 133   histogram_enabled = value;
 134 #ifndef RISCV_ENABLE_HISTOGRAM
 135   if (value) {
 136     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 137     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 138   }
 139 #endif
 140 }
 141
 142 void processor_t::reset(bool value)
 143 {
 144   if (run == !value)
 145     return;
 146   run = !value;
 147
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 void processor_t::raise_interrupt(reg_t which)
 158 {
 159   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 160 }
 161
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt()
 172 {
 173   reg_t pending_interrupts = state.mip & state.mie;
 174
 175   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 176   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 177   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 178
 179   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 180   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 181   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (enabled_interrupts)
 184     raise_interrupt(ctz(enabled_interrupts));
 185 }
 186
 187 static bool validate_priv(reg_t priv)
 188 {
 189   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 190 }
 191
 192 void processor_t::set_privilege(reg_t prv)
 193 {
 194   assert(validate_priv(prv));
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   state.dcsr.cause = cause;
 202   state.dcsr.prv = state.prv;
 203   set_privilege(PRV_M);
 204   state.dpc = state.pc;
 205   state.pc = DEBUG_ROM_START;
 206   //debug = true; // TODO
 207 }
 208
 209 void processor_t::take_trap(trap_t& t, reg_t epc)
 210 {
 211   if (debug) {
 212     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 213             id, t.name(), epc);
 214     if (t.has_badaddr())
 215       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 216           t.get_badaddr());
 217   }
 218
 219   if (t.cause() == CAUSE_BREAKPOINT && (
 220               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 221               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 222               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 223               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 224     enter_debug_mode(DCSR_CAUSE_SWBP);
 225     return;
 226   }
 227
 228   if (state.dcsr.cause) {
 229     state.pc = DEBUG_ROM_EXCEPTION;
 230     return;
 231   }
 232
 233   // by default, trap to M-mode, unless delegated to S-mode
 234   reg_t bit = t.cause();
 235   reg_t deleg = state.medeleg;
 236   if (bit & ((reg_t)1 << (max_xlen-1)))
 237     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 238   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 239     // handle the trap in S-mode
 240     state.pc = state.stvec;
 241     state.scause = t.cause();
 242     state.sepc = epc;
 243     if (t.has_badaddr())
 244       state.sbadaddr = t.get_badaddr();
 245
 246     reg_t s = state.mstatus;
 247     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 248     s = set_field(s, MSTATUS_SPP, state.prv);
 249     s = set_field(s, MSTATUS_SIE, 0);
 250     set_csr(CSR_MSTATUS, s);
 251     set_privilege(PRV_S);
 252   } else {
 253     state.pc = state.mtvec;
 254     state.mepc = epc;
 255     state.mcause = t.cause();
 256     if (t.has_badaddr())
 257       state.mbadaddr = t.get_badaddr();
 258
 259     reg_t s = state.mstatus;
 260     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 261     s = set_field(s, MSTATUS_MPP, state.prv);
 262     s = set_field(s, MSTATUS_MIE, 0);
 263     set_csr(CSR_MSTATUS, s);
 264     set_privilege(PRV_M);
 265   }
 266
 267   yield_load_reservation();
 268 }
 269
 270 void processor_t::disasm(insn_t insn)
 271 {
 272   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 273   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 274           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 275 }
 276
 277 static bool validate_vm(int max_xlen, reg_t vm)
 278 {
 279   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 280     return true;
 281   if (max_xlen == 32 && vm == VM_SV32)
 282     return true;
 283   return vm == VM_MBARE;
 284 }
 285
 286 int processor_t::paddr_bits()
 287 {
 288   assert(xlen == max_xlen);
 289   return max_xlen == 64 ? 50 : 34;
 290 }
 291
 292 void processor_t::set_csr(int which, reg_t val)
 293 {
 294   val = zext_xlen(val);
 295   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 296   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 297   switch (which)
 298   {
 299     case CSR_FFLAGS:
 300       dirty_fp_state;
 301       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 302       break;
 303     case CSR_FRM:
 304       dirty_fp_state;
 305       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 306       break;
 307     case CSR_FCSR:
 308       dirty_fp_state;
 309       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 310       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 311       break;
 312     case CSR_MSTATUS: {
 313       if ((val ^ state.mstatus) &
 314           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 315         mmu->flush_tlb();
 316
 317       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 318                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 319                  | (ext ? MSTATUS_XS : 0);
 320
 321       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 322         mask |= MSTATUS_VM;
 323       if (validate_priv(get_field(val, MSTATUS_MPP)))
 324         mask |= MSTATUS_MPP;
 325
 326       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 327
 328       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 329       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 330       if (max_xlen == 32)
 331         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 332       else
 333         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 334
 335       // spike supports the notion of xlen < max_xlen, but current priv spec
 336       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 337       xlen = max_xlen;
 338       break;
 339     }
 340     case CSR_MIP: {
 341       reg_t mask = MIP_SSIP | MIP_STIP;
 342       state.mip = (state.mip & ~mask) | (val & mask);
 343       break;
 344     }
 345     case CSR_MIE:
 346       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 347       break;
 348     case CSR_MIDELEG:
 349       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 350       break;
 351     case CSR_MEDELEG: {
 352       reg_t mask = 0;
 353 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 354 #include "encoding.h"
 355 #undef DECLARE_CAUSE
 356       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 357       break;
 358     }
 359     case CSR_MUCOUNTEREN:
 360       state.mucounteren = val & 7;
 361       break;
 362     case CSR_MSCOUNTEREN:
 363       state.mscounteren = val & 7;
 364       break;
 365     case CSR_SSTATUS: {
 366       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 367                  | SSTATUS_XS | SSTATUS_PUM;
 368       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 369     }
 370     case CSR_SIP:
 371       return set_csr(CSR_MIP,
 372                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 373     case CSR_SIE:
 374       return set_csr(CSR_MIE,
 375                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 376     case CSR_SPTBR: {
 377       // upper bits of sptbr are the ASID; we only support ASID = 0
 378       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 379       break;
 380     }
 381     case CSR_SEPC: state.sepc = val; break;
 382     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 383     case CSR_SSCRATCH: state.sscratch = val; break;
 384     case CSR_SCAUSE: state.scause = val; break;
 385     case CSR_SBADADDR: state.sbadaddr = val; break;
 386     case CSR_MEPC: state.mepc = val; break;
 387     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 388     case CSR_MSCRATCH: state.mscratch = val; break;
 389     case CSR_MCAUSE: state.mcause = val; break;
 390     case CSR_MBADADDR: state.mbadaddr = val; break;
 391     case CSR_DCSR:
 392       state.dcsr.prv = get_field(val, DCSR_PRV);
 393       state.dcsr.step = get_field(val, DCSR_STEP);
 394       // TODO: ndreset and fullreset
 395       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 396       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 397       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 398       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 399       state.dcsr.halt = get_field(val, DCSR_HALT);
 400       break;
 401     case CSR_DPC:
 402       state.dpc = val;
 403       break;
 404     case CSR_DSCRATCH:
 405       state.dscratch = val;
 406       break;
 407   }
 408 }
 409
 410 reg_t processor_t::get_csr(int which)
 411 {
 412   switch (which)
 413   {
 414     case CSR_FFLAGS:
 415       require_fp;
 416       if (!supports_extension('F'))
 417         break;
 418       return state.fflags;
 419     case CSR_FRM:
 420       require_fp;
 421       if (!supports_extension('F'))
 422         break;
 423       return state.frm;
 424     case CSR_FCSR:
 425       require_fp;
 426       if (!supports_extension('F'))
 427         break;
 428       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 429     case CSR_TIME:
 430     case CSR_INSTRET:
 431     case CSR_CYCLE:
 432       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 433         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 434       break;
 435     case CSR_STIME:
 436     case CSR_SINSTRET:
 437     case CSR_SCYCLE:
 438       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 439         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 440       break;
 441     case CSR_MUCOUNTEREN: return state.mucounteren;
 442     case CSR_MSCOUNTEREN: return state.mscounteren;
 443     case CSR_MUCYCLE_DELTA: return 0;
 444     case CSR_MUTIME_DELTA: return 0;
 445     case CSR_MUINSTRET_DELTA: return 0;
 446     case CSR_MSCYCLE_DELTA: return 0;
 447     case CSR_MSTIME_DELTA: return 0;
 448     case CSR_MSINSTRET_DELTA: return 0;
 449     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 450     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 451     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 452     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 453     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 454     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 455     case CSR_MCYCLE: return state.minstret;
 456     case CSR_MINSTRET: return state.minstret;
 457     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 458     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 459     case CSR_SSTATUS: {
 460       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 461                  | SSTATUS_XS | SSTATUS_PUM;
 462       reg_t sstatus = state.mstatus & mask;
 463       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 464           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 465         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 466       return sstatus;
 467     }
 468     case CSR_SIP: return state.mip & state.mideleg;
 469     case CSR_SIE: return state.mie & state.mideleg;
 470     case CSR_SEPC: return state.sepc;
 471     case CSR_SBADADDR: return state.sbadaddr;
 472     case CSR_STVEC: return state.stvec;
 473     case CSR_SCAUSE:
 474       if (max_xlen > xlen)
 475         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 476       return state.scause;
 477     case CSR_SPTBR: return state.sptbr;
 478     case CSR_SSCRATCH: return state.sscratch;
 479     case CSR_MSTATUS: return state.mstatus;
 480     case CSR_MIP: return state.mip;
 481     case CSR_MIE: return state.mie;
 482     case CSR_MEPC: return state.mepc;
 483     case CSR_MSCRATCH: return state.mscratch;
 484     case CSR_MCAUSE: return state.mcause;
 485     case CSR_MBADADDR: return state.mbadaddr;
 486     case CSR_MISA: return isa;
 487     case CSR_MARCHID: return 0;
 488     case CSR_MIMPID: return 0;
 489     case CSR_MVENDORID: return 0;
 490     case CSR_MHARTID: return id;
 491     case CSR_MTVEC: return state.mtvec;
 492     case CSR_MEDELEG: return state.medeleg;
 493     case CSR_MIDELEG: return state.mideleg;
 494     case CSR_TDRSELECT: return 0;
 495     case CSR_DCSR:
 496       {
 497         uint32_t v = 0;
 498         v = set_field(v, DCSR_XDEBUGVER, 1);
 499         v = set_field(v, DCSR_HWBPCOUNT, 0);
 500         v = set_field(v, DCSR_NDRESET, 0);
 501         v = set_field(v, DCSR_FULLRESET, 0);
 502         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 503         v = set_field(v, DCSR_STEP, state.dcsr.step);
 504         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 505         v = set_field(v, DCSR_STOPCYCLE, 0);
 506         v = set_field(v, DCSR_STOPTIME, 0);
 507         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 508         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 509         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 510         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 511         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 512         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 513         return v;
 514       }
 515     case CSR_DPC:
 516       return state.dpc;
 517     case CSR_DSCRATCH:
 518       return state.dscratch;
 519   }
 520   throw trap_illegal_instruction();
 521 }
 522
 523 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 524 {
 525   throw trap_illegal_instruction();
 526 }
 527
 528 insn_func_t processor_t::decode_insn(insn_t insn)
 529 {
 530   // look up opcode in hash table
 531   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 532   insn_desc_t desc = opcode_cache[idx];
 533
 534   if (unlikely(insn.bits() != desc.match)) {
 535     // fall back to linear search
 536     insn_desc_t* p = &instructions[0];
 537     while ((insn.bits() & p->mask) != p->match)
 538       p++;
 539     desc = *p;
 540
 541     if (p->mask != 0 && p > &instructions[0]) {
 542       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 543         // move to front of opcode list to reduce miss penalty
 544         while (--p >= &instructions[0])
 545           *(p+1) = *p;
 546         instructions[0] = desc;
 547       }
 548     }
 549
 550     opcode_cache[idx] = desc;
 551     opcode_cache[idx].match = insn.bits();
 552   }
 553
 554   return xlen == 64 ? desc.rv64 : desc.rv32;
 555 }
 556
 557 void processor_t::register_insn(insn_desc_t desc)
 558 {
 559   instructions.push_back(desc);
 560 }
 561
 562 void processor_t::build_opcode_map()
 563 {
 564   struct cmp {
 565     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 566       if (lhs.match == rhs.match)
 567         return lhs.mask > rhs.mask;
 568       return lhs.match > rhs.match;
 569     }
 570   };
 571   std::sort(instructions.begin(), instructions.end(), cmp());
 572
 573   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 574     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 575 }
 576
 577 void processor_t::register_extension(extension_t* x)
 578 {
 579   for (auto insn : x->get_instructions())
 580     register_insn(insn);
 581   build_opcode_map();
 582   for (auto disasm_insn : x->get_disasms())
 583     disassembler->add_insn(disasm_insn);
 584   if (ext != NULL)
 585     throw std::logic_error("only one extension may be registered");
 586   ext = x;
 587   x->set_processor(this);
 588 }
 589
 590 void processor_t::register_base_instructions()
 591 {
 592   #define DECLARE_INSN(name, match, mask) \
 593     insn_bits_t name##_match = (match), name##_mask = (mask);
 594   #include "encoding.h"
 595   #undef DECLARE_INSN
 596
 597   #define DEFINE_INSN(name) \
 598     REGISTER_INSN(this, name, name##_match, name##_mask)
 599   #include "insn_list.h"
 600   #undef DEFINE_INSN
 601
 602   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 603   build_opcode_map();
 604 }
 605
 606 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 607 {
 608   return false;
 609 }
 610
 611 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 612 {
 613   switch (addr)
 614   {
 615     case 0:
 616       state.mip &= ~MIP_MSIP;
 617       if (bytes[0] & 1)
 618         state.mip |= MIP_MSIP;
 619       return true;
 620
 621     default:
 622       return false;
 623   }
 624 }