riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   load_reservation = -1;
 122   tselect = 0;
 123   for (unsigned int i = 0; i < num_triggers; i++)
 124     mcontrol[i].type = 2;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset()
 146 {
 147   state.reset();
 148   state.dcsr.halt = halt_on_reset;
 149   halt_on_reset = false;
 150   set_csr(CSR_MSTATUS, state.mstatus);
 151
 152   if (ext)
 153     ext->reset(); // reset the extension
 154 }
 155
 156 // Count number of contiguous 0 bits starting from the LSB.
 157 static int ctz(reg_t val)
 158 {
 159   int res = 0;
 160   if (val)
 161     while ((val & 1) == 0)
 162       val >>= 1, res++;
 163   return res;
 164 }
 165
 166 void processor_t::take_interrupt(reg_t pending_interrupts)
 167 {
 168   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 169   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 170   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 171
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 174   if (enabled_interrupts == 0)
 175     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (state.dcsr.cause == 0 && enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 static int xlen_to_uxl(int xlen)
 182 {
 183   if (xlen == 32)
 184     return 1;
 185   if (xlen == 64)
 186     return 2;
 187   abort();
 188 }
 189
 190 void processor_t::set_privilege(reg_t prv)
 191 {
 192   assert(prv <= PRV_M);
 193   if (prv == PRV_H)
 194     prv = PRV_U;
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   state.dcsr.cause = cause;
 202   state.dcsr.prv = state.prv;
 203   set_privilege(PRV_M);
 204   state.dpc = state.pc;
 205   state.pc = DEBUG_ROM_ENTRY;
 206 }
 207
 208 void processor_t::take_trap(trap_t& t, reg_t epc)
 209 {
 210   if (debug) {
 211     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 212             id, t.name(), epc);
 213     if (t.has_badaddr())
 214       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 215           t.get_badaddr());
 216   }
 217
 218   if (state.dcsr.cause) {
 219     if (t.cause() == CAUSE_BREAKPOINT) {
 220       state.pc = DEBUG_ROM_ENTRY;
 221     } else {
 222       state.pc = DEBUG_ROM_TVEC;
 223     }
 224     return;
 225   }
 226
 227   if (t.cause() == CAUSE_BREAKPOINT && (
 228               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 229               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 230               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 231               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 232     enter_debug_mode(DCSR_CAUSE_SWBP);
 233     return;
 234   }
 235
 236   // by default, trap to M-mode, unless delegated to S-mode
 237   reg_t bit = t.cause();
 238   reg_t deleg = state.medeleg;
 239   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 240   if (interrupt)
 241     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 242   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 243     // handle the trap in S-mode
 244     state.pc = state.stvec;
 245     state.scause = t.cause();
 246     state.sepc = epc;
 247     if (t.has_badaddr())
 248       state.sbadaddr = t.get_badaddr();
 249
 250     reg_t s = state.mstatus;
 251     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 252     s = set_field(s, MSTATUS_SPP, state.prv);
 253     s = set_field(s, MSTATUS_SIE, 0);
 254     set_csr(CSR_MSTATUS, s);
 255     set_privilege(PRV_S);
 256   } else {
 257     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 258     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 259     state.mepc = epc;
 260     state.mcause = t.cause();
 261     if (t.has_badaddr())
 262       state.mbadaddr = t.get_badaddr();
 263
 264     reg_t s = state.mstatus;
 265     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 266     s = set_field(s, MSTATUS_MPP, state.prv);
 267     s = set_field(s, MSTATUS_MIE, 0);
 268     set_csr(CSR_MSTATUS, s);
 269     set_privilege(PRV_M);
 270   }
 271
 272   yield_load_reservation();
 273 }
 274
 275 void processor_t::disasm(insn_t insn)
 276 {
 277   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 278   if (last_pc != state.pc || last_bits != bits) {
 279     if (executions != 1) {
 280       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 281     }
 282
 283     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 284             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 285     last_pc = state.pc;
 286     last_bits = bits;
 287     executions = 1;
 288   } else {
 289     executions++;
 290   }
 291 }
 292
 293 int processor_t::paddr_bits()
 294 {
 295   assert(xlen == max_xlen);
 296   return max_xlen == 64 ? 50 : 34;
 297 }
 298
 299 void processor_t::set_csr(int which, reg_t val)
 300 {
 301   val = zext_xlen(val);
 302   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 303   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 304   switch (which)
 305   {
 306     case CSR_FFLAGS:
 307       dirty_fp_state;
 308       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 309       break;
 310     case CSR_FRM:
 311       dirty_fp_state;
 312       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 313       break;
 314     case CSR_FCSR:
 315       dirty_fp_state;
 316       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 317       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 318       break;
 319     case CSR_MSTATUS: {
 320       if ((val ^ state.mstatus) &
 321           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 322         mmu->flush_tlb();
 323
 324       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 325                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 326                  | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 327                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 328                  (ext ? MSTATUS_XS : 0);
 329
 330       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 331
 332       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 333       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 334       if (max_xlen == 32)
 335         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 336       else
 337         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 338
 339       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 340       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 341       // U-XLEN == S-XLEN == M-XLEN
 342       xlen = max_xlen;
 343       break;
 344     }
 345     case CSR_MIP: {
 346       reg_t mask = MIP_SSIP | MIP_STIP;
 347       state.mip = (state.mip & ~mask) | (val & mask);
 348       break;
 349     }
 350     case CSR_MIE:
 351       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 352       break;
 353     case CSR_MIDELEG:
 354       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 355       break;
 356     case CSR_MEDELEG: {
 357       reg_t mask = 0;
 358 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 359 #include "encoding.h"
 360 #undef DECLARE_CAUSE
 361       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 362       break;
 363     }
 364     case CSR_MINSTRET:
 365     case CSR_MCYCLE:
 366       if (xlen == 32)
 367         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 368       else
 369         state.minstret = val;
 370       break;
 371     case CSR_MINSTRETH:
 372     case CSR_MCYCLEH:
 373       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 374       break;
 375     case CSR_SCOUNTEREN:
 376       state.scounteren = val;
 377       break;
 378     case CSR_MCOUNTEREN:
 379       state.mcounteren = val;
 380       break;
 381     case CSR_SSTATUS: {
 382       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 383                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 384       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 385     }
 386     case CSR_SIP: {
 387       reg_t mask = MIP_SSIP & state.mideleg;
 388       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 389     }
 390     case CSR_SIE:
 391       return set_csr(CSR_MIE,
 392                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 393     case CSR_SPTBR: {
 394       mmu->flush_tlb();
 395       if (max_xlen == 32)
 396         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 397       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 398                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 399                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 400         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 401       break;
 402     }
 403     case CSR_SEPC: state.sepc = val; break;
 404     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 405     case CSR_SSCRATCH: state.sscratch = val; break;
 406     case CSR_SCAUSE: state.scause = val; break;
 407     case CSR_SBADADDR: state.sbadaddr = val; break;
 408     case CSR_MEPC: state.mepc = val; break;
 409     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 410     case CSR_MSCRATCH: state.mscratch = val; break;
 411     case CSR_MCAUSE: state.mcause = val; break;
 412     case CSR_MBADADDR: state.mbadaddr = val; break;
 413     case CSR_MISA: {
 414       if (!(val & (1L << ('F' - 'A'))))
 415         val &= ~(1L << ('D' - 'A'));
 416
 417       // allow MAFDC bits in MISA to be modified
 418       reg_t mask = 0;
 419       mask |= 1L << ('M' - 'A');
 420       mask |= 1L << ('A' - 'A');
 421       mask |= 1L << ('F' - 'A');
 422       mask |= 1L << ('D' - 'A');
 423       mask |= 1L << ('C' - 'A');
 424       mask &= max_isa;
 425
 426       isa = (val & mask) | (isa & ~mask);
 427       break;
 428     }
 429     case CSR_TSELECT:
 430       if (val < state.num_triggers) {
 431         state.tselect = val;
 432       }
 433       break;
 434     case CSR_TDATA1:
 435       {
 436         mcontrol_t *mc = &state.mcontrol[state.tselect];
 437         if (mc->dmode && !state.dcsr.cause) {
 438           break;
 439         }
 440         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 441         mc->select = get_field(val, MCONTROL_SELECT);
 442         mc->timing = get_field(val, MCONTROL_TIMING);
 443         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 444         mc->chain = get_field(val, MCONTROL_CHAIN);
 445         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 446         mc->m = get_field(val, MCONTROL_M);
 447         mc->h = get_field(val, MCONTROL_H);
 448         mc->s = get_field(val, MCONTROL_S);
 449         mc->u = get_field(val, MCONTROL_U);
 450         mc->execute = get_field(val, MCONTROL_EXECUTE);
 451         mc->store = get_field(val, MCONTROL_STORE);
 452         mc->load = get_field(val, MCONTROL_LOAD);
 453         // Assume we're here because of csrw.
 454         if (mc->execute)
 455           mc->timing = 0;
 456         trigger_updated();
 457       }
 458       break;
 459     case CSR_TDATA2:
 460       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 461         break;
 462       }
 463       if (state.tselect < state.num_triggers) {
 464         state.tdata2[state.tselect] = val;
 465       }
 466       break;
 467     case CSR_DCSR:
 468       state.dcsr.prv = get_field(val, DCSR_PRV);
 469       state.dcsr.step = get_field(val, DCSR_STEP);
 470       // TODO: ndreset and fullreset
 471       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 472       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 473       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 474       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 475       state.dcsr.halt = get_field(val, DCSR_HALT);
 476       break;
 477     case CSR_DPC:
 478       state.dpc = val;
 479       break;
 480     case CSR_DSCRATCH:
 481       state.dscratch = val;
 482       break;
 483   }
 484 }
 485
 486 reg_t processor_t::get_csr(int which)
 487 {
 488   uint32_t ctr_en = -1;
 489   if (state.prv < PRV_M)
 490     ctr_en &= state.mcounteren;
 491   if (state.prv < PRV_S)
 492     ctr_en &= state.scounteren;
 493   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 494
 495   if (ctr_ok) {
 496     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 497       return 0;
 498     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 499       return 0;
 500   }
 501   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 502     return 0;
 503   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 504     return 0;
 505   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 506     return 0;
 507
 508   switch (which)
 509   {
 510     case CSR_FFLAGS:
 511       require_fp;
 512       if (!supports_extension('F'))
 513         break;
 514       return state.fflags;
 515     case CSR_FRM:
 516       require_fp;
 517       if (!supports_extension('F'))
 518         break;
 519       return state.frm;
 520     case CSR_FCSR:
 521       require_fp;
 522       if (!supports_extension('F'))
 523         break;
 524       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 525     case CSR_INSTRET:
 526     case CSR_CYCLE:
 527       if (ctr_ok)
 528         return state.minstret;
 529       break;
 530     case CSR_MINSTRET:
 531     case CSR_MCYCLE:
 532       return state.minstret;
 533     case CSR_MINSTRETH:
 534     case CSR_MCYCLEH:
 535       if (xlen == 32)
 536         return state.minstret >> 32;
 537       break;
 538     case CSR_SCOUNTEREN: return state.scounteren;
 539     case CSR_MCOUNTEREN: return state.mcounteren;
 540     case CSR_SSTATUS: {
 541       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 542                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 543       reg_t sstatus = state.mstatus & mask;
 544       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 545           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 546         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 547       return sstatus;
 548     }
 549     case CSR_SIP: return state.mip & state.mideleg;
 550     case CSR_SIE: return state.mie & state.mideleg;
 551     case CSR_SEPC: return state.sepc;
 552     case CSR_SBADADDR: return state.sbadaddr;
 553     case CSR_STVEC: return state.stvec;
 554     case CSR_SCAUSE:
 555       if (max_xlen > xlen)
 556         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 557       return state.scause;
 558     case CSR_SPTBR:
 559       if (get_field(state.mstatus, MSTATUS_TVM))
 560         require_privilege(PRV_M);
 561       return state.sptbr;
 562     case CSR_SSCRATCH: return state.sscratch;
 563     case CSR_MSTATUS: return state.mstatus;
 564     case CSR_MIP: return state.mip;
 565     case CSR_MIE: return state.mie;
 566     case CSR_MEPC: return state.mepc;
 567     case CSR_MSCRATCH: return state.mscratch;
 568     case CSR_MCAUSE: return state.mcause;
 569     case CSR_MBADADDR: return state.mbadaddr;
 570     case CSR_MISA: return isa;
 571     case CSR_MARCHID: return 0;
 572     case CSR_MIMPID: return 0;
 573     case CSR_MVENDORID: return 0;
 574     case CSR_MHARTID: return id;
 575     case CSR_MTVEC: return state.mtvec;
 576     case CSR_MEDELEG: return state.medeleg;
 577     case CSR_MIDELEG: return state.mideleg;
 578     case CSR_TSELECT: return state.tselect;
 579     case CSR_TDATA1:
 580       if (state.tselect < state.num_triggers) {
 581         reg_t v = 0;
 582         mcontrol_t *mc = &state.mcontrol[state.tselect];
 583         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 584         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 585         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 586         v = set_field(v, MCONTROL_SELECT, mc->select);
 587         v = set_field(v, MCONTROL_TIMING, mc->timing);
 588         v = set_field(v, MCONTROL_ACTION, mc->action);
 589         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 590         v = set_field(v, MCONTROL_MATCH, mc->match);
 591         v = set_field(v, MCONTROL_M, mc->m);
 592         v = set_field(v, MCONTROL_H, mc->h);
 593         v = set_field(v, MCONTROL_S, mc->s);
 594         v = set_field(v, MCONTROL_U, mc->u);
 595         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 596         v = set_field(v, MCONTROL_STORE, mc->store);
 597         v = set_field(v, MCONTROL_LOAD, mc->load);
 598         return v;
 599       } else {
 600         return 0;
 601       }
 602       break;
 603     case CSR_TDATA2:
 604       if (state.tselect < state.num_triggers) {
 605         return state.tdata2[state.tselect];
 606       } else {
 607         return 0;
 608       }
 609       break;
 610     case CSR_TDATA3: return 0;
 611     case CSR_DCSR:
 612       {
 613         uint32_t v = 0;
 614         v = set_field(v, DCSR_XDEBUGVER, 1);
 615         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 616         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 617         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 618         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 619         v = set_field(v, DCSR_STOPCYCLE, 0);
 620         v = set_field(v, DCSR_STOPTIME, 0);
 621         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 622         v = set_field(v, DCSR_STEP, state.dcsr.step);
 623         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 624         return v;
 625       }
 626     case CSR_DPC:
 627       return state.dpc;
 628     case CSR_DSCRATCH:
 629       return state.dscratch;
 630   }
 631   throw trap_illegal_instruction(0);
 632 }
 633
 634 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 635 {
 636   throw trap_illegal_instruction(0);
 637 }
 638
 639 insn_func_t processor_t::decode_insn(insn_t insn)
 640 {
 641   // look up opcode in hash table
 642   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 643   insn_desc_t desc = opcode_cache[idx];
 644
 645   if (unlikely(insn.bits() != desc.match)) {
 646     // fall back to linear search
 647     insn_desc_t* p = &instructions[0];
 648     while ((insn.bits() & p->mask) != p->match)
 649       p++;
 650     desc = *p;
 651
 652     if (p->mask != 0 && p > &instructions[0]) {
 653       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 654         // move to front of opcode list to reduce miss penalty
 655         while (--p >= &instructions[0])
 656           *(p+1) = *p;
 657         instructions[0] = desc;
 658       }
 659     }
 660
 661     opcode_cache[idx] = desc;
 662     opcode_cache[idx].match = insn.bits();
 663   }
 664
 665   return xlen == 64 ? desc.rv64 : desc.rv32;
 666 }
 667
 668 void processor_t::register_insn(insn_desc_t desc)
 669 {
 670   instructions.push_back(desc);
 671 }
 672
 673 void processor_t::build_opcode_map()
 674 {
 675   struct cmp {
 676     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 677       if (lhs.match == rhs.match)
 678         return lhs.mask > rhs.mask;
 679       return lhs.match > rhs.match;
 680     }
 681   };
 682   std::sort(instructions.begin(), instructions.end(), cmp());
 683
 684   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 685     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 686 }
 687
 688 void processor_t::register_extension(extension_t* x)
 689 {
 690   for (auto insn : x->get_instructions())
 691     register_insn(insn);
 692   build_opcode_map();
 693   for (auto disasm_insn : x->get_disasms())
 694     disassembler->add_insn(disasm_insn);
 695   if (ext != NULL)
 696     throw std::logic_error("only one extension may be registered");
 697   ext = x;
 698   x->set_processor(this);
 699 }
 700
 701 void processor_t::register_base_instructions()
 702 {
 703   #define DECLARE_INSN(name, match, mask) \
 704     insn_bits_t name##_match = (match), name##_mask = (mask);
 705   #include "encoding.h"
 706   #undef DECLARE_INSN
 707
 708   #define DEFINE_INSN(name) \
 709     REGISTER_INSN(this, name, name##_match, name##_mask)
 710   #include "insn_list.h"
 711   #undef DEFINE_INSN
 712
 713   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 714   build_opcode_map();
 715 }
 716
 717 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 718 {
 719   switch (addr)
 720   {
 721     case 0:
 722       if (len <= 4) {
 723         memset(bytes, 0, len);
 724         bytes[0] = get_field(state.mip, MIP_MSIP);
 725         return true;
 726       }
 727       break;
 728   }
 729
 730   return false;
 731 }
 732
 733 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 734 {
 735   switch (addr)
 736   {
 737     case 0:
 738       if (len <= 4) {
 739         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 740         return true;
 741       }
 742       break;
 743   }
 744
 745   return false;
 746 }
 747
 748 void processor_t::trigger_updated()
 749 {
 750   mmu->flush_tlb();
 751   mmu->check_triggers_fetch = false;
 752   mmu->check_triggers_load = false;
 753   mmu->check_triggers_store = false;
 754
 755   for (unsigned i = 0; i < state.num_triggers; i++) {
 756     if (state.mcontrol[i].execute) {
 757       mmu->check_triggers_fetch = true;
 758     }
 759     if (state.mcontrol[i].load) {
 760       mmu->check_triggers_load = true;
 761     }
 762     if (state.mcontrol[i].store) {
 763       mmu->check_triggers_store = true;
 764     }
 765   }
 766 }