riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa = "rv" + std::to_string(max_xlen) + p;
  86   cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     cpuid |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107 }
 108
 109 void state_t::reset()
 110 {
 111   memset(this, 0, sizeof(*this));
 112   prv = PRV_M;
 113   pc = DEFAULT_RSTVEC;
 114   load_reservation = -1;
 115 }
 116
 117 void processor_t::set_debug(bool value)
 118 {
 119   debug = value;
 120   if (ext)
 121     ext->set_debug(value);
 122 }
 123
 124 void processor_t::set_histogram(bool value)
 125 {
 126   histogram_enabled = value;
 127 #ifndef RISCV_ENABLE_HISTOGRAM
 128   if (value) {
 129     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 130     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 131   }
 132 #endif
 133 }
 134
 135 void processor_t::reset(bool value)
 136 {
 137   if (run == !value)
 138     return;
 139   run = !value;
 140
 141   state.reset();
 142   set_csr(CSR_MSTATUS, state.mstatus);
 143
 144   if (ext)
 145     ext->reset(); // reset the extension
 146 }
 147
 148 void processor_t::raise_interrupt(reg_t which)
 149 {
 150   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 151 }
 152
 153 static int ctz(reg_t val)
 154 {
 155   int res = 0;
 156   if (val)
 157     while ((val & 1) == 0)
 158       val >>= 1, res++;
 159   return res;
 160 }
 161
 162 void processor_t::take_interrupt()
 163 {
 164   check_timer();
 165
 166   reg_t interrupts = state.mip & state.mie;
 167
 168   reg_t m_interrupts = interrupts & ~state.mideleg;
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
 171     raise_interrupt(ctz(m_interrupts));
 172
 173   reg_t s_interrupts = interrupts & state.mideleg;
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
 176     raise_interrupt(ctz(s_interrupts));
 177 }
 178
 179 void processor_t::check_timer()
 180 {
 181   if (sim->rtc >= state.mtimecmp)
 182     state.mip |= MIP_MTIP;
 183 }
 184
 185 static bool validate_priv(reg_t priv)
 186 {
 187   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 188 }
 189
 190 void processor_t::set_privilege(reg_t prv)
 191 {
 192   assert(validate_priv(prv));
 193   mmu->flush_tlb();
 194   state.prv = prv;
 195 }
 196
 197 void processor_t::take_trap(trap_t& t, reg_t epc)
 198 {
 199   if (debug)
 200     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 201             id, t.name(), epc);
 202
 203   // by default, trap to M-mode, unless delegated to S-mode
 204   reg_t bit = t.cause();
 205   reg_t deleg = state.medeleg;
 206   if (bit & ((reg_t)1 << (max_xlen-1)))
 207     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 208   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 209     // handle the trap in S-mode
 210     state.pc = state.stvec;
 211     state.scause = t.cause();
 212     state.sepc = epc;
 213     if (t.has_badaddr())
 214       state.sbadaddr = t.get_badaddr();
 215
 216     reg_t s = state.mstatus;
 217     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 218     s = set_field(s, MSTATUS_SPP, state.prv);
 219     s = set_field(s, MSTATUS_SIE, 0);
 220     set_csr(CSR_MSTATUS, s);
 221     set_privilege(PRV_S);
 222   } else {
 223     state.pc = DEFAULT_MTVEC;
 224     state.mcause = t.cause();
 225     state.mepc = epc;
 226     if (t.has_badaddr())
 227       state.mbadaddr = t.get_badaddr();
 228
 229     reg_t s = state.mstatus;
 230     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 231     s = set_field(s, MSTATUS_MPP, state.prv);
 232     s = set_field(s, MSTATUS_MIE, 0);
 233     set_csr(CSR_MSTATUS, s);
 234     set_privilege(PRV_M);
 235   }
 236
 237   yield_load_reservation();
 238 }
 239
 240 void processor_t::disasm(insn_t insn)
 241 {
 242   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 243   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 244           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 245 }
 246
 247 static bool validate_vm(int max_xlen, reg_t vm)
 248 {
 249   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 250     return true;
 251   if (max_xlen == 32 && vm == VM_SV32)
 252     return true;
 253   return vm == VM_MBARE;
 254 }
 255
 256 void processor_t::set_csr(int which, reg_t val)
 257 {
 258   val = zext_xlen(val);
 259   reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
 260   reg_t s_ints = MIP_SSIP | MIP_STIP;
 261   switch (which)
 262   {
 263     case CSR_FFLAGS:
 264       dirty_fp_state;
 265       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 266       break;
 267     case CSR_FRM:
 268       dirty_fp_state;
 269       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 270       break;
 271     case CSR_FCSR:
 272       dirty_fp_state;
 273       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 274       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 275       break;
 276     case CSR_MTIME:
 277     case CSR_STIMEW:
 278       // this implementation ignores writes to MTIME
 279       break;
 280     case CSR_MTIMEH:
 281     case CSR_STIMEHW:
 282       // this implementation ignores writes to MTIME
 283       break;
 284     case CSR_TIMEW:
 285       val -= sim->rtc;
 286       if (xlen == 32)
 287         state.sutime_delta = val | (state.sutime_delta >> 32 << 32);
 288       else
 289         state.sutime_delta = val;
 290       break;
 291     case CSR_TIMEHW:
 292       val = ((val << 32) - sim->rtc) >> 32;
 293       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 294       break;
 295     case CSR_CYCLEW:
 296     case CSR_INSTRETW:
 297       val -= state.minstret;
 298       if (xlen == 32)
 299         state.suinstret_delta = val | (state.suinstret_delta >> 32 << 32);
 300       else
 301         state.suinstret_delta = val;
 302       break;
 303     case CSR_CYCLEHW:
 304     case CSR_INSTRETHW:
 305       val = ((val << 32) - state.minstret) >> 32;
 306       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 307       break;
 308     case CSR_MSTATUS: {
 309       if ((val ^ state.mstatus) &
 310           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 311         mmu->flush_tlb();
 312
 313       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 314                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 315                  | (ext ? MSTATUS_XS : 0);
 316
 317       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 318         mask |= MSTATUS_VM;
 319       if (validate_priv(get_field(val, MSTATUS_MPP)))
 320         mask |= MSTATUS_MPP;
 321
 322       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 323
 324       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 325       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 326       if (max_xlen == 32)
 327         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 328       else
 329         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 330
 331       // spike supports the notion of xlen < max_xlen, but current priv spec
 332       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 333       xlen = max_xlen;
 334       break;
 335     }
 336     case CSR_MIP: {
 337       reg_t mask = all_ints &~ MIP_MTIP;
 338       state.mip = (state.mip & ~mask) | (val & mask);
 339       break;
 340     }
 341     case CSR_MIPI:
 342       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 343       break;
 344     case CSR_MIE:
 345       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 346       break;
 347     case CSR_MIDELEG:
 348       state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
 349       break;
 350     case CSR_MEDELEG: {
 351       reg_t mask = 0;
 352 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 353 #include "encoding.h"
 354 #undef DECLARE_CAUSE
 355       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 356       break;
 357     }
 358     case CSR_SSTATUS: {
 359       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 360                  | SSTATUS_XS | SSTATUS_PUM;
 361       set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 362       break;
 363     }
 364     case CSR_SIP: {
 365       reg_t mask = s_ints &~ MIP_STIP;
 366       state.mip = (state.mip & ~mask) | (val & mask);
 367       break;
 368     }
 369     case CSR_SIE: {
 370       reg_t mask = s_ints;
 371       state.mie = (state.mie & ~mask) | (val & mask);
 372       break;
 373     }
 374     case CSR_SEPC: state.sepc = val; break;
 375     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 376     case CSR_SPTBR: state.sptbr = val; break;
 377     case CSR_SSCRATCH: state.sscratch = val; break;
 378     case CSR_SCAUSE: state.scause = val; break;
 379     case CSR_SBADADDR: state.sbadaddr = val; break;
 380     case CSR_MEPC: state.mepc = val; break;
 381     case CSR_MSCRATCH: state.mscratch = val; break;
 382     case CSR_MCAUSE: state.mcause = val; break;
 383     case CSR_MBADADDR: state.mbadaddr = val; break;
 384     case CSR_MTIMECMP:
 385       state.mip &= ~MIP_MTIP;
 386       state.mtimecmp = val;
 387       break;
 388     case CSR_MTOHOST:
 389       if (state.tohost == 0)
 390         state.tohost = val;
 391       break;
 392     case CSR_MFROMHOST:
 393       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 394       state.fromhost = val;
 395       break;
 396   }
 397 }
 398
 399 reg_t processor_t::get_csr(int which)
 400 {
 401   switch (which)
 402   {
 403     case CSR_FFLAGS:
 404       require_fp;
 405       if (!supports_extension('F'))
 406         break;
 407       return state.fflags;
 408     case CSR_FRM:
 409       require_fp;
 410       if (!supports_extension('F'))
 411         break;
 412       return state.frm;
 413     case CSR_FCSR:
 414       require_fp;
 415       if (!supports_extension('F'))
 416         break;
 417       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 418     case CSR_MTIME:
 419     case CSR_STIME:
 420     case CSR_STIMEW:
 421       return sim->rtc;
 422     case CSR_MTIMEH:
 423     case CSR_STIMEH:
 424     case CSR_STIMEHW:
 425       return sim->rtc >> 32;
 426     case CSR_TIME:
 427     case CSR_TIMEW:
 428       return sim->rtc + state.sutime_delta;
 429     case CSR_CYCLE:
 430     case CSR_CYCLEW:
 431     case CSR_INSTRET:
 432     case CSR_INSTRETW:
 433       return state.minstret + state.suinstret_delta;
 434     case CSR_TIMEH:
 435     case CSR_TIMEHW:
 436       if (xlen == 64)
 437         break;
 438       return (sim->rtc + state.sutime_delta) >> 32;
 439     case CSR_CYCLEH:
 440     case CSR_INSTRETH:
 441     case CSR_CYCLEHW:
 442     case CSR_INSTRETHW:
 443       if (xlen == 64)
 444         break;
 445       return (state.minstret + state.suinstret_delta) >> 32;
 446     case CSR_SSTATUS: {
 447       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 448                  | SSTATUS_XS | SSTATUS_PUM;
 449       reg_t sstatus = state.mstatus & mask;
 450       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 451           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 452         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 453       return sstatus;
 454     }
 455     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 456     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 457     case CSR_SEPC: return state.sepc;
 458     case CSR_SBADADDR: return state.sbadaddr;
 459     case CSR_STVEC: return state.stvec;
 460     case CSR_SCAUSE:
 461       if (max_xlen > xlen)
 462         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 463       return state.scause;
 464     case CSR_SPTBR: return state.sptbr;
 465     case CSR_SASID: return 0;
 466     case CSR_SSCRATCH: return state.sscratch;
 467     case CSR_MSTATUS: return state.mstatus;
 468     case CSR_MIP: return state.mip;
 469     case CSR_MIPI: return 0;
 470     case CSR_MIE: return state.mie;
 471     case CSR_MEPC: return state.mepc;
 472     case CSR_MSCRATCH: return state.mscratch;
 473     case CSR_MCAUSE: return state.mcause;
 474     case CSR_MBADADDR: return state.mbadaddr;
 475     case CSR_MTIMECMP: return state.mtimecmp;
 476     case CSR_MCPUID: return cpuid;
 477     case CSR_MIMPID: return IMPL_ROCKET;
 478     case CSR_MHARTID: return id;
 479     case CSR_MTVEC: return DEFAULT_MTVEC;
 480     case CSR_MEDELEG: return state.medeleg;
 481     case CSR_MIDELEG: return state.mideleg;
 482     case CSR_MTOHOST:
 483       sim->get_htif()->tick(); // not necessary, but faster
 484       return state.tohost;
 485     case CSR_MFROMHOST:
 486       sim->get_htif()->tick(); // not necessary, but faster
 487       return state.fromhost;
 488     case CSR_MIOBASE: return sim->memsz;
 489     case CSR_UARCH0:
 490     case CSR_UARCH1:
 491     case CSR_UARCH2:
 492     case CSR_UARCH3:
 493     case CSR_UARCH4:
 494     case CSR_UARCH5:
 495     case CSR_UARCH6:
 496     case CSR_UARCH7:
 497     case CSR_UARCH8:
 498     case CSR_UARCH9:
 499     case CSR_UARCH10:
 500     case CSR_UARCH11:
 501     case CSR_UARCH12:
 502     case CSR_UARCH13:
 503     case CSR_UARCH14:
 504     case CSR_UARCH15:
 505       return 0;
 506   }
 507   throw trap_illegal_instruction();
 508 }
 509
 510 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 511 {
 512   throw trap_illegal_instruction();
 513 }
 514
 515 insn_func_t processor_t::decode_insn(insn_t insn)
 516 {
 517   // look up opcode in hash table
 518   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 519   insn_desc_t desc = opcode_cache[idx];
 520
 521   if (unlikely(insn.bits() != desc.match)) {
 522     // fall back to linear search
 523     insn_desc_t* p = &instructions[0];
 524     while ((insn.bits() & p->mask) != p->match)
 525       p++;
 526     desc = *p;
 527
 528     if (p->mask != 0 && p > &instructions[0]) {
 529       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 530         // move to front of opcode list to reduce miss penalty
 531         while (--p >= &instructions[0])
 532           *(p+1) = *p;
 533         instructions[0] = desc;
 534       }
 535     }
 536
 537     opcode_cache[idx] = desc;
 538     opcode_cache[idx].match = insn.bits();
 539   }
 540
 541   return xlen == 64 ? desc.rv64 : desc.rv32;
 542 }
 543
 544 void processor_t::register_insn(insn_desc_t desc)
 545 {
 546   instructions.push_back(desc);
 547 }
 548
 549 void processor_t::build_opcode_map()
 550 {
 551   struct cmp {
 552     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 553       if (lhs.match == rhs.match)
 554         return lhs.mask > rhs.mask;
 555       return lhs.match > rhs.match;
 556     }
 557   };
 558   std::sort(instructions.begin(), instructions.end(), cmp());
 559
 560   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 561     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 562 }
 563
 564 void processor_t::register_extension(extension_t* x)
 565 {
 566   for (auto insn : x->get_instructions())
 567     register_insn(insn);
 568   build_opcode_map();
 569   for (auto disasm_insn : x->get_disasms())
 570     disassembler->add_insn(disasm_insn);
 571   if (ext != NULL)
 572     throw std::logic_error("only one extension may be registered");
 573   ext = x;
 574   x->set_processor(this);
 575 }
 576
 577 void processor_t::register_base_instructions()
 578 {
 579   #define DECLARE_INSN(name, match, mask) \
 580     insn_bits_t name##_match = (match), name##_mask = (mask);
 581   #include "encoding.h"
 582   #undef DECLARE_INSN
 583
 584   #define DEFINE_INSN(name) \
 585     REGISTER_INSN(this, name, name##_match, name##_mask)
 586   #include "insn_list.h"
 587   #undef DEFINE_INSN
 588
 589   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 590   build_opcode_map();
 591 }
 592
 593 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 594 {
 595   try {
 596     auto res = get_csr(addr / (max_xlen / 8));
 597     memcpy(bytes, &res, len);
 598     return true;
 599   } catch (trap_illegal_instruction& t) {
 600     return false;
 601   }
 602 }
 603
 604 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 605 {
 606   try {
 607     reg_t value = 0;
 608     memcpy(&value, bytes, len);
 609     set_csr(addr / (max_xlen / 8), value);
 610     return true;
 611   } catch (trap_illegal_instruction& t) {
 612     return false;
 613   }
 614 }