riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121   tselect = 0;
 122   for (unsigned int i = 0; i < num_triggers; i++) {
 123     mcontrol[i].type = 2;
 124     mcontrol[i].action = ACTION_NONE;
 125     tdata1[i] = 0;
 126   }
 127 }
 128
 129 void processor_t::set_debug(bool value)
 130 {
 131   debug = value;
 132   if (ext)
 133     ext->set_debug(value);
 134 }
 135
 136 void processor_t::set_histogram(bool value)
 137 {
 138   histogram_enabled = value;
 139 #ifndef RISCV_ENABLE_HISTOGRAM
 140   if (value) {
 141     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 142     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 143   }
 144 #endif
 145 }
 146
 147 void processor_t::reset()
 148 {
 149   state.reset();
 150   state.dcsr.halt = halt_on_reset;
 151   halt_on_reset = false;
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 void processor_t::raise_interrupt(reg_t which)
 159 {
 160   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 161 }
 162
 163 // Count number of contiguous 0 bits starting from the LSB.
 164 static int ctz(reg_t val)
 165 {
 166   int res = 0;
 167   if (val)
 168     while ((val & 1) == 0)
 169       val >>= 1, res++;
 170   return res;
 171 }
 172
 173 void processor_t::take_interrupt()
 174 {
 175   reg_t pending_interrupts = state.mip & state.mie;
 176
 177   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 178   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 179   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 180
 181   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 182   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 183   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 184
 185   if (enabled_interrupts)
 186     raise_interrupt(ctz(enabled_interrupts));
 187 }
 188
 189 void processor_t::set_privilege(reg_t prv)
 190 {
 191   assert(prv <= PRV_M);
 192   if (prv == PRV_H)
 193     prv = PRV_U;
 194   mmu->flush_tlb();
 195   state.prv = prv;
 196 }
 197
 198 void processor_t::enter_debug_mode(uint8_t cause)
 199 {
 200   state.dcsr.cause = cause;
 201   state.dcsr.prv = state.prv;
 202   set_privilege(PRV_M);
 203   state.dpc = state.pc;
 204   state.pc = DEBUG_ROM_START;
 205 }
 206
 207 void processor_t::take_trap(trap_t& t, reg_t epc)
 208 {
 209   if (debug) {
 210     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 211             id, t.name(), epc);
 212     if (t.has_badaddr())
 213       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 214           t.get_badaddr());
 215   }
 216
 217   if (t.cause() == CAUSE_BREAKPOINT && (
 218               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 219               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 220               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 221               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 222     enter_debug_mode(DCSR_CAUSE_SWBP);
 223     return;
 224   }
 225
 226   if (state.dcsr.cause) {
 227     state.pc = DEBUG_ROM_EXCEPTION;
 228     return;
 229   }
 230
 231   // by default, trap to M-mode, unless delegated to S-mode
 232   reg_t bit = t.cause();
 233   reg_t deleg = state.medeleg;
 234   if (bit & ((reg_t)1 << (max_xlen-1)))
 235     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 236   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 237     // handle the trap in S-mode
 238     state.pc = state.stvec;
 239     state.scause = t.cause();
 240     state.sepc = epc;
 241     if (t.has_badaddr())
 242       state.sbadaddr = t.get_badaddr();
 243
 244     reg_t s = state.mstatus;
 245     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 246     s = set_field(s, MSTATUS_SPP, state.prv);
 247     s = set_field(s, MSTATUS_SIE, 0);
 248     set_csr(CSR_MSTATUS, s);
 249     set_privilege(PRV_S);
 250   } else {
 251     state.pc = state.mtvec;
 252     state.mepc = epc;
 253     state.mcause = t.cause();
 254     if (t.has_badaddr())
 255       state.mbadaddr = t.get_badaddr();
 256
 257     reg_t s = state.mstatus;
 258     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 259     s = set_field(s, MSTATUS_MPP, state.prv);
 260     s = set_field(s, MSTATUS_MIE, 0);
 261     set_csr(CSR_MSTATUS, s);
 262     set_privilege(PRV_M);
 263   }
 264
 265   yield_load_reservation();
 266 }
 267
 268 void processor_t::disasm(insn_t insn)
 269 {
 270   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 271   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 272           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 273 }
 274
 275 static bool validate_vm(int max_xlen, reg_t vm)
 276 {
 277   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 278     return true;
 279   if (max_xlen == 32 && vm == VM_SV32)
 280     return true;
 281   return vm == VM_MBARE;
 282 }
 283
 284 int processor_t::paddr_bits()
 285 {
 286   assert(xlen == max_xlen);
 287   return max_xlen == 64 ? 50 : 34;
 288 }
 289
 290 void processor_t::set_csr(int which, reg_t val)
 291 {
 292   val = zext_xlen(val);
 293   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 294   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 295   switch (which)
 296   {
 297     case CSR_FFLAGS:
 298       dirty_fp_state;
 299       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 300       break;
 301     case CSR_FRM:
 302       dirty_fp_state;
 303       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 304       break;
 305     case CSR_FCSR:
 306       dirty_fp_state;
 307       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 308       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 309       break;
 310     case CSR_MSTATUS: {
 311       if ((val ^ state.mstatus) &
 312           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 313         mmu->flush_tlb();
 314
 315       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 316                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 317                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 318
 319       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 320         mask |= MSTATUS_VM;
 321
 322       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 323
 324       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 325       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 326       if (max_xlen == 32)
 327         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 328       else
 329         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 330
 331       // spike supports the notion of xlen < max_xlen, but current priv spec
 332       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 333       xlen = max_xlen;
 334       break;
 335     }
 336     case CSR_MIP: {
 337       reg_t mask = MIP_SSIP | MIP_STIP;
 338       state.mip = (state.mip & ~mask) | (val & mask);
 339       break;
 340     }
 341     case CSR_MIE:
 342       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 343       break;
 344     case CSR_MIDELEG:
 345       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 346       break;
 347     case CSR_MEDELEG: {
 348       reg_t mask = 0;
 349 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 350 #include "encoding.h"
 351 #undef DECLARE_CAUSE
 352       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 353       break;
 354     }
 355     case CSR_MUCOUNTEREN:
 356       state.mucounteren = val & 7;
 357       break;
 358     case CSR_MSCOUNTEREN:
 359       state.mscounteren = val & 7;
 360       break;
 361     case CSR_SSTATUS: {
 362       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 363                  | SSTATUS_XS | SSTATUS_PUM;
 364       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 365     }
 366     case CSR_SIP:
 367       return set_csr(CSR_MIP,
 368                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 369     case CSR_SIE:
 370       return set_csr(CSR_MIE,
 371                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 372     case CSR_SPTBR: {
 373       // upper bits of sptbr are the ASID; we only support ASID = 0
 374       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 375       break;
 376     }
 377     case CSR_SEPC: state.sepc = val; break;
 378     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 379     case CSR_SSCRATCH: state.sscratch = val; break;
 380     case CSR_SCAUSE: state.scause = val; break;
 381     case CSR_SBADADDR: state.sbadaddr = val; break;
 382     case CSR_MEPC: state.mepc = val; break;
 383     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 384     case CSR_MSCRATCH: state.mscratch = val; break;
 385     case CSR_MCAUSE: state.mcause = val; break;
 386     case CSR_MBADADDR: state.mbadaddr = val; break;
 387     case CSR_TSELECT: state.tselect = val; break;
 388     case CSR_TDATA0:
 389       if (state.tselect < state.num_triggers) {
 390         mcontrol_t *mc = &state.mcontrol[state.tselect];
 391         mc->select = get_field(val, MCONTROL_SELECT);
 392         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 393         mc->chain = get_field(val, MCONTROL_CHAIN);
 394         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 395         mc->m = get_field(val, MCONTROL_M);
 396         mc->h = get_field(val, MCONTROL_H);
 397         mc->s = get_field(val, MCONTROL_S);
 398         mc->u = get_field(val, MCONTROL_U);
 399         mc->execute = get_field(val, MCONTROL_EXECUTE);
 400         mc->store = get_field(val, MCONTROL_STORE);
 401         mc->load = get_field(val, MCONTROL_LOAD);
 402         // Assume we're here because of csrw.
 403         trigger_updated();
 404       }
 405       break;
 406     case CSR_TDATA1:
 407       if (state.tselect < state.num_triggers) {
 408         state.tdata1[state.tselect] = val;
 409       }
 410       break;
 411     case CSR_DCSR:
 412       state.dcsr.prv = get_field(val, DCSR_PRV);
 413       state.dcsr.step = get_field(val, DCSR_STEP);
 414       // TODO: ndreset and fullreset
 415       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 416       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 417       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 418       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 419       state.dcsr.halt = get_field(val, DCSR_HALT);
 420       break;
 421     case CSR_DPC:
 422       state.dpc = val;
 423       break;
 424     case CSR_DSCRATCH:
 425       state.dscratch = val;
 426       break;
 427   }
 428 }
 429
 430 reg_t processor_t::get_csr(int which)
 431 {
 432   switch (which)
 433   {
 434     case CSR_FFLAGS:
 435       require_fp;
 436       if (!supports_extension('F'))
 437         break;
 438       return state.fflags;
 439     case CSR_FRM:
 440       require_fp;
 441       if (!supports_extension('F'))
 442         break;
 443       return state.frm;
 444     case CSR_FCSR:
 445       require_fp;
 446       if (!supports_extension('F'))
 447         break;
 448       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 449     case CSR_TIME:
 450     case CSR_INSTRET:
 451     case CSR_CYCLE:
 452       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 453         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 454       break;
 455     case CSR_STIME:
 456     case CSR_SINSTRET:
 457     case CSR_SCYCLE:
 458       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 459         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 460       break;
 461     case CSR_MUCOUNTEREN: return state.mucounteren;
 462     case CSR_MSCOUNTEREN: return state.mscounteren;
 463     case CSR_MUCYCLE_DELTA: return 0;
 464     case CSR_MUTIME_DELTA: return 0;
 465     case CSR_MUINSTRET_DELTA: return 0;
 466     case CSR_MSCYCLE_DELTA: return 0;
 467     case CSR_MSTIME_DELTA: return 0;
 468     case CSR_MSINSTRET_DELTA: return 0;
 469     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 470     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 471     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 472     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 473     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 474     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 475     case CSR_MCYCLE: return state.minstret;
 476     case CSR_MINSTRET: return state.minstret;
 477     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 478     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 479     case CSR_SSTATUS: {
 480       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 481                  | SSTATUS_XS | SSTATUS_PUM;
 482       reg_t sstatus = state.mstatus & mask;
 483       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 484           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 485         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 486       return sstatus;
 487     }
 488     case CSR_SIP: return state.mip & state.mideleg;
 489     case CSR_SIE: return state.mie & state.mideleg;
 490     case CSR_SEPC: return state.sepc;
 491     case CSR_SBADADDR: return state.sbadaddr;
 492     case CSR_STVEC: return state.stvec;
 493     case CSR_SCAUSE:
 494       if (max_xlen > xlen)
 495         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 496       return state.scause;
 497     case CSR_SPTBR: return state.sptbr;
 498     case CSR_SSCRATCH: return state.sscratch;
 499     case CSR_MSTATUS: return state.mstatus;
 500     case CSR_MIP: return state.mip;
 501     case CSR_MIE: return state.mie;
 502     case CSR_MEPC: return state.mepc;
 503     case CSR_MSCRATCH: return state.mscratch;
 504     case CSR_MCAUSE: return state.mcause;
 505     case CSR_MBADADDR: return state.mbadaddr;
 506     case CSR_MISA: return isa;
 507     case CSR_MARCHID: return 0;
 508     case CSR_MIMPID: return 0;
 509     case CSR_MVENDORID: return 0;
 510     case CSR_MHARTID: return id;
 511     case CSR_MTVEC: return state.mtvec;
 512     case CSR_MEDELEG: return state.medeleg;
 513     case CSR_MIDELEG: return state.mideleg;
 514     case CSR_TSELECT: return state.tselect;
 515     case CSR_TDATA0:
 516       if (state.tselect < state.num_triggers) {
 517         reg_t v = 0;
 518         mcontrol_t *mc = &state.mcontrol[state.tselect];
 519         v = set_field(v, 0xfL << (xlen-4), mc->type);
 520         v = set_field(v, 0x3fL << (xlen-10), mc->maskmax);
 521         v = set_field(v, MCONTROL_SELECT, mc->select);
 522         v = set_field(v, MCONTROL_ACTION, mc->action);
 523         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 524         v = set_field(v, MCONTROL_MATCH, mc->match);
 525         v = set_field(v, MCONTROL_M, mc->m);
 526         v = set_field(v, MCONTROL_H, mc->h);
 527         v = set_field(v, MCONTROL_S, mc->s);
 528         v = set_field(v, MCONTROL_U, mc->u);
 529         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 530         v = set_field(v, MCONTROL_STORE, mc->store);
 531         v = set_field(v, MCONTROL_LOAD, mc->load);
 532         return v;
 533       } else {
 534         return 0;
 535       }
 536       break;
 537     case CSR_TDATA1:
 538       if (state.tselect < state.num_triggers) {
 539         return state.tdata1[state.tselect];
 540       } else {
 541         return 0;
 542       }
 543       break;
 544     case CSR_DCSR:
 545       {
 546         uint32_t v = 0;
 547         v = set_field(v, DCSR_XDEBUGVER, 1);
 548         v = set_field(v, DCSR_NDRESET, 0);
 549         v = set_field(v, DCSR_FULLRESET, 0);
 550         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 551         v = set_field(v, DCSR_STEP, state.dcsr.step);
 552         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 553         v = set_field(v, DCSR_STOPCYCLE, 0);
 554         v = set_field(v, DCSR_STOPTIME, 0);
 555         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 556         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 557         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 558         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 559         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 560         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 561         return v;
 562       }
 563     case CSR_DPC:
 564       return state.dpc;
 565     case CSR_DSCRATCH:
 566       return state.dscratch;
 567   }
 568   throw trap_illegal_instruction();
 569 }
 570
 571 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 572 {
 573   throw trap_illegal_instruction();
 574 }
 575
 576 insn_func_t processor_t::decode_insn(insn_t insn)
 577 {
 578   // look up opcode in hash table
 579   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 580   insn_desc_t desc = opcode_cache[idx];
 581
 582   if (unlikely(insn.bits() != desc.match)) {
 583     // fall back to linear search
 584     insn_desc_t* p = &instructions[0];
 585     while ((insn.bits() & p->mask) != p->match)
 586       p++;
 587     desc = *p;
 588
 589     if (p->mask != 0 && p > &instructions[0]) {
 590       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 591         // move to front of opcode list to reduce miss penalty
 592         while (--p >= &instructions[0])
 593           *(p+1) = *p;
 594         instructions[0] = desc;
 595       }
 596     }
 597
 598     opcode_cache[idx] = desc;
 599     opcode_cache[idx].match = insn.bits();
 600   }
 601
 602   return xlen == 64 ? desc.rv64 : desc.rv32;
 603 }
 604
 605 void processor_t::register_insn(insn_desc_t desc)
 606 {
 607   instructions.push_back(desc);
 608 }
 609
 610 void processor_t::build_opcode_map()
 611 {
 612   struct cmp {
 613     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 614       if (lhs.match == rhs.match)
 615         return lhs.mask > rhs.mask;
 616       return lhs.match > rhs.match;
 617     }
 618   };
 619   std::sort(instructions.begin(), instructions.end(), cmp());
 620
 621   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 622     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 623 }
 624
 625 void processor_t::register_extension(extension_t* x)
 626 {
 627   for (auto insn : x->get_instructions())
 628     register_insn(insn);
 629   build_opcode_map();
 630   for (auto disasm_insn : x->get_disasms())
 631     disassembler->add_insn(disasm_insn);
 632   if (ext != NULL)
 633     throw std::logic_error("only one extension may be registered");
 634   ext = x;
 635   x->set_processor(this);
 636 }
 637
 638 void processor_t::register_base_instructions()
 639 {
 640   #define DECLARE_INSN(name, match, mask) \
 641     insn_bits_t name##_match = (match), name##_mask = (mask);
 642   #include "encoding.h"
 643   #undef DECLARE_INSN
 644
 645   #define DEFINE_INSN(name) \
 646     REGISTER_INSN(this, name, name##_match, name##_mask)
 647   #include "insn_list.h"
 648   #undef DEFINE_INSN
 649
 650   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 651   build_opcode_map();
 652 }
 653
 654 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 655 {
 656   return false;
 657 }
 658
 659 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 660 {
 661   switch (addr)
 662   {
 663     case 0:
 664       state.mip &= ~MIP_MSIP;
 665       if (bytes[0] & 1)
 666         state.mip |= MIP_MSIP;
 667       return true;
 668
 669     default:
 670       return false;
 671   }
 672 }
 673
 674 void processor_t::trigger_updated()
 675 {
 676   mmu->flush_tlb();
 677   mmu->check_triggers_fetch = false;
 678   mmu->check_triggers_load = false;
 679   mmu->check_triggers_store = false;
 680
 681   for (unsigned i = 0; i < state.num_triggers; i++) {
 682     if (state.mcontrol[i].action == ACTION_NONE)
 683       continue;
 684     if (state.mcontrol[i].execute) {
 685       mmu->check_triggers_fetch = true;
 686     }
 687     if (state.mcontrol[i].load) {
 688       mmu->check_triggers_load = true;
 689     }
 690     if (state.mcontrol[i].store) {
 691       mmu->check_triggers_store = true;
 692     }
 693   }
 694 }