riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  24   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  25     id(id), run(false), debug(false)
  26 {
  27   parse_isa_string(isa);
  28
  29   mmu = new mmu_t(sim, this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     isa |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107
 108   // advertise support for supervisor and user modes
 109   isa |= 1L << ('s' - 'a');
 110   isa |= 1L << ('u' - 'a');
 111 }
 112
 113 void state_t::reset()
 114 {
 115   memset(this, 0, sizeof(*this));
 116   prv = PRV_M;
 117   pc = DEFAULT_RSTVEC;
 118   mtvec = DEFAULT_MTVEC;
 119   load_reservation = -1;
 120 }
 121
 122 void processor_t::set_debug_int()
 123 {
 124   state.dcsr.debugint = true;
 125 }
 126
 127 void processor_t::set_debug(bool value)
 128 {
 129   debug = value;
 130   if (ext)
 131     ext->set_debug(value);
 132 }
 133
 134 void processor_t::set_histogram(bool value)
 135 {
 136   histogram_enabled = value;
 137 #ifndef RISCV_ENABLE_HISTOGRAM
 138   if (value) {
 139     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 140     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 141   }
 142 #endif
 143 }
 144
 145 void processor_t::reset(bool value)
 146 {
 147   if (run == !value)
 148     return;
 149   run = !value;
 150
 151   state.reset();
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 void processor_t::raise_interrupt(reg_t which)
 159 {
 160   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 161 }
 162
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt()
 173 {
 174   reg_t pending_interrupts = state.mip & state.mie;
 175
 176   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 177   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 178   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 179
 180   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 181   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 182   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 183
 184   if (enabled_interrupts)
 185     raise_interrupt(ctz(enabled_interrupts));
 186 }
 187
 188 static bool validate_priv(reg_t priv)
 189 {
 190   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 191 }
 192
 193 void processor_t::set_privilege(reg_t prv)
 194 {
 195   assert(validate_priv(prv));
 196   mmu->flush_tlb();
 197   state.prv = prv;
 198 }
 199
 200 void processor_t::enter_debug_mode(uint8_t cause)
 201 {
 202   state.dcsr.cause = cause;
 203   state.dpc = state.pc;
 204   state.pc = DEBUG_ROM_ENTRY;
 205 }
 206
 207 void processor_t::take_trap(trap_t& t, reg_t epc)
 208 {
 209   if (debug)
 210     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 211             id, t.name(), epc);
 212
 213   if (t.cause() == CAUSE_BREAKPOINT &&
 214           sim->gdbserver && sim->gdbserver->connected()) {
 215     enter_debug_mode(DCSR_CAUSE_SWBP);
 216     return;
 217   }
 218
 219   // by default, trap to M-mode, unless delegated to S-mode
 220   reg_t bit = t.cause();
 221   reg_t deleg = state.medeleg;
 222   if (bit & ((reg_t)1 << (max_xlen-1)))
 223     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 224   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 225     // handle the trap in S-mode
 226     state.pc = state.stvec;
 227     state.scause = t.cause();
 228     state.sepc = epc;
 229     if (t.has_badaddr())
 230       state.sbadaddr = t.get_badaddr();
 231
 232     reg_t s = state.mstatus;
 233     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 234     s = set_field(s, MSTATUS_SPP, state.prv);
 235     s = set_field(s, MSTATUS_SIE, 0);
 236     set_csr(CSR_MSTATUS, s);
 237     set_privilege(PRV_S);
 238   } else {
 239     state.pc = state.mtvec;
 240     state.mcause = t.cause();
 241     state.mepc = epc;
 242     if (t.has_badaddr())
 243       state.mbadaddr = t.get_badaddr();
 244
 245     reg_t s = state.mstatus;
 246     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 247     s = set_field(s, MSTATUS_MPP, state.prv);
 248     s = set_field(s, MSTATUS_MIE, 0);
 249     set_csr(CSR_MSTATUS, s);
 250     set_privilege(PRV_M);
 251   }
 252
 253   yield_load_reservation();
 254 }
 255
 256 void processor_t::disasm(insn_t insn)
 257 {
 258   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 259   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 260           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 261 }
 262
 263 static bool validate_vm(int max_xlen, reg_t vm)
 264 {
 265   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 266     return true;
 267   if (max_xlen == 32 && vm == VM_SV32)
 268     return true;
 269   return vm == VM_MBARE;
 270 }
 271
 272 void processor_t::set_csr(int which, reg_t val)
 273 {
 274   val = zext_xlen(val);
 275   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 276   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 277   switch (which)
 278   {
 279     case CSR_FFLAGS:
 280       dirty_fp_state;
 281       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 282       break;
 283     case CSR_FRM:
 284       dirty_fp_state;
 285       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 286       break;
 287     case CSR_FCSR:
 288       dirty_fp_state;
 289       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 290       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 291       break;
 292     case CSR_MSTATUS: {
 293       if ((val ^ state.mstatus) &
 294           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 295         mmu->flush_tlb();
 296
 297       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 298                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 299                  | (ext ? MSTATUS_XS : 0);
 300
 301       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 302         mask |= MSTATUS_VM;
 303       if (validate_priv(get_field(val, MSTATUS_MPP)))
 304         mask |= MSTATUS_MPP;
 305
 306       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 307
 308       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 309       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 310       if (max_xlen == 32)
 311         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 312       else
 313         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 314
 315       // spike supports the notion of xlen < max_xlen, but current priv spec
 316       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 317       xlen = max_xlen;
 318       break;
 319     }
 320     case CSR_MIP: {
 321       reg_t mask = MIP_SSIP | MIP_STIP;
 322       state.mip = (state.mip & ~mask) | (val & mask);
 323       break;
 324     }
 325     case CSR_MIE:
 326       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 327       break;
 328     case CSR_MIDELEG:
 329       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 330       break;
 331     case CSR_MEDELEG: {
 332       reg_t mask = 0;
 333 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 334 #include "encoding.h"
 335 #undef DECLARE_CAUSE
 336       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 337       break;
 338     }
 339     case CSR_MUCOUNTEREN:
 340       state.mucounteren = val & 7;
 341       break;
 342     case CSR_MSCOUNTEREN:
 343       state.mscounteren = val & 7;
 344       break;
 345     case CSR_SSTATUS: {
 346       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 347                  | SSTATUS_XS | SSTATUS_PUM;
 348       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 349     }
 350     case CSR_SIP:
 351       return set_csr(CSR_MIP,
 352                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 353     case CSR_SIE:
 354       return set_csr(CSR_MIE,
 355                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 356     case CSR_SEPC: state.sepc = val; break;
 357     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 358     case CSR_SPTBR: state.sptbr = val; break;
 359     case CSR_SSCRATCH: state.sscratch = val; break;
 360     case CSR_SCAUSE: state.scause = val; break;
 361     case CSR_SBADADDR: state.sbadaddr = val; break;
 362     case CSR_MEPC: state.mepc = val; break;
 363     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 364     case CSR_MSCRATCH: state.mscratch = val; break;
 365     case CSR_MCAUSE: state.mcause = val; break;
 366     case CSR_MBADADDR: state.mbadaddr = val; break;
 367     case DCSR_ADDRESS:
 368       state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
 369       state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
 370       // TODO: ndreset and fullreset
 371       state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
 372       state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
 373       state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
 374       state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
 375       state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
 376       break;
 377     case DPC_ADDRESS:
 378       state.dpc = val;
 379       break;
 380     case DSCRATCH_ADDRESS:
 381       state.dscratch = val;
 382       break;
 383   }
 384 }
 385
 386 reg_t processor_t::get_csr(int which)
 387 {
 388   switch (which)
 389   {
 390     case CSR_FFLAGS:
 391       require_fp;
 392       if (!supports_extension('F'))
 393         break;
 394       return state.fflags;
 395     case CSR_FRM:
 396       require_fp;
 397       if (!supports_extension('F'))
 398         break;
 399       return state.frm;
 400     case CSR_FCSR:
 401       require_fp;
 402       if (!supports_extension('F'))
 403         break;
 404       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 405     case CSR_TIME:
 406     case CSR_INSTRET:
 407     case CSR_CYCLE:
 408       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 409         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 410       break;
 411     case CSR_STIME:
 412     case CSR_SINSTRET:
 413     case CSR_SCYCLE:
 414       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 415         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 416       break;
 417     case CSR_MUCOUNTEREN: return state.mucounteren;
 418     case CSR_MSCOUNTEREN: return state.mscounteren;
 419     case CSR_MUCYCLE_DELTA: return 0;
 420     case CSR_MUTIME_DELTA: return 0;
 421     case CSR_MUINSTRET_DELTA: return 0;
 422     case CSR_MSCYCLE_DELTA: return 0;
 423     case CSR_MSTIME_DELTA: return 0;
 424     case CSR_MSINSTRET_DELTA: return 0;
 425     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 426     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 427     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 428     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 429     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 430     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 431     case CSR_MCYCLE: return state.minstret;
 432     case CSR_MINSTRET: return state.minstret;
 433     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 434     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 435     case CSR_SSTATUS: {
 436       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 437                  | SSTATUS_XS | SSTATUS_PUM;
 438       reg_t sstatus = state.mstatus & mask;
 439       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 440           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 441         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 442       return sstatus;
 443     }
 444     case CSR_SIP: return state.mip & state.mideleg;
 445     case CSR_SIE: return state.mie & state.mideleg;
 446     case CSR_SEPC: return state.sepc;
 447     case CSR_SBADADDR: return state.sbadaddr;
 448     case CSR_STVEC: return state.stvec;
 449     case CSR_SCAUSE:
 450       if (max_xlen > xlen)
 451         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 452       return state.scause;
 453     case CSR_SPTBR: return state.sptbr;
 454     case CSR_SASID: return 0;
 455     case CSR_SSCRATCH: return state.sscratch;
 456     case CSR_MSTATUS: return state.mstatus;
 457     case CSR_MIP: return state.mip;
 458     case CSR_MIE: return state.mie;
 459     case CSR_MEPC: return state.mepc;
 460     case CSR_MSCRATCH: return state.mscratch;
 461     case CSR_MCAUSE: return state.mcause;
 462     case CSR_MBADADDR: return state.mbadaddr;
 463     case CSR_MISA: return isa;
 464     case CSR_MARCHID: return 0;
 465     case CSR_MIMPID: return 0;
 466     case CSR_MVENDORID: return 0;
 467     case CSR_MHARTID: return id;
 468     case CSR_MTVEC: return state.mtvec;
 469     case CSR_MEDELEG: return state.medeleg;
 470     case CSR_MIDELEG: return state.mideleg;
 471     case DCSR_ADDRESS:
 472       return
 473           (1 << DCSR_XDEBUGVER_OFFSET) |
 474           (0 << DCSR_HWBPCOUNT_OFFSET) |
 475           (0 << DCSR_NDRESET_OFFSET) |
 476           (0 << DCSR_FULLRESET_OFFSET) |
 477           (state.dcsr.prv << DCSR_PRV_OFFSET) |
 478           (state.dcsr.step << DCSR_STEP_OFFSET) |
 479           (state.dcsr.debugint << DCSR_DEBUGINT_OFFSET) |
 480           (0 << DCSR_STOPCYCLE_OFFSET) |
 481           (0 << DCSR_STOPTIME_OFFSET) |
 482           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
 483           (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
 484           (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
 485           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
 486           (state.dcsr.halt << DCSR_HALT_OFFSET) |
 487           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
 488     case DPC_ADDRESS:
 489       return state.dpc;
 490     case DSCRATCH_ADDRESS:
 491       return state.dscratch;
 492   }
 493   throw trap_illegal_instruction();
 494 }
 495
 496 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 497 {
 498   throw trap_illegal_instruction();
 499 }
 500
 501 insn_func_t processor_t::decode_insn(insn_t insn)
 502 {
 503   // look up opcode in hash table
 504   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 505   insn_desc_t desc = opcode_cache[idx];
 506
 507   if (unlikely(insn.bits() != desc.match)) {
 508     // fall back to linear search
 509     insn_desc_t* p = &instructions[0];
 510     while ((insn.bits() & p->mask) != p->match)
 511       p++;
 512     desc = *p;
 513
 514     if (p->mask != 0 && p > &instructions[0]) {
 515       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 516         // move to front of opcode list to reduce miss penalty
 517         while (--p >= &instructions[0])
 518           *(p+1) = *p;
 519         instructions[0] = desc;
 520       }
 521     }
 522
 523     opcode_cache[idx] = desc;
 524     opcode_cache[idx].match = insn.bits();
 525   }
 526
 527   return xlen == 64 ? desc.rv64 : desc.rv32;
 528 }
 529
 530 void processor_t::register_insn(insn_desc_t desc)
 531 {
 532   instructions.push_back(desc);
 533 }
 534
 535 void processor_t::build_opcode_map()
 536 {
 537   struct cmp {
 538     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 539       if (lhs.match == rhs.match)
 540         return lhs.mask > rhs.mask;
 541       return lhs.match > rhs.match;
 542     }
 543   };
 544   std::sort(instructions.begin(), instructions.end(), cmp());
 545
 546   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 547     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 548 }
 549
 550 void processor_t::register_extension(extension_t* x)
 551 {
 552   for (auto insn : x->get_instructions())
 553     register_insn(insn);
 554   build_opcode_map();
 555   for (auto disasm_insn : x->get_disasms())
 556     disassembler->add_insn(disasm_insn);
 557   if (ext != NULL)
 558     throw std::logic_error("only one extension may be registered");
 559   ext = x;
 560   x->set_processor(this);
 561 }
 562
 563 void processor_t::register_base_instructions()
 564 {
 565   #define DECLARE_INSN(name, match, mask) \
 566     insn_bits_t name##_match = (match), name##_mask = (mask);
 567   #include "encoding.h"
 568   #undef DECLARE_INSN
 569
 570   #define DEFINE_INSN(name) \
 571     REGISTER_INSN(this, name, name##_match, name##_mask)
 572   #include "insn_list.h"
 573   #undef DEFINE_INSN
 574
 575   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 576   build_opcode_map();
 577 }
 578
 579 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 580 {
 581   return false;
 582 }
 583
 584 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 585 {
 586   switch (addr)
 587   {
 588     case 0:
 589       state.mip &= ~MIP_MSIP;
 590       if (bytes[0] & 1)
 591         state.mip |= MIP_MSIP;
 592       return true;
 593
 594     default:
 595       return false;
 596   }
 597 }