riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   mtvec = DEFAULT_MTVEC;
 122   load_reservation = -1;
 123   tselect = 0;
 124   for (unsigned int i = 0; i < num_triggers; i++)
 125     mcontrol[i].type = 2;
 126 }
 127
 128 void processor_t::set_debug(bool value)
 129 {
 130   debug = value;
 131   if (ext)
 132     ext->set_debug(value);
 133 }
 134
 135 void processor_t::set_histogram(bool value)
 136 {
 137   histogram_enabled = value;
 138 #ifndef RISCV_ENABLE_HISTOGRAM
 139   if (value) {
 140     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 141     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 142   }
 143 #endif
 144 }
 145
 146 void processor_t::reset()
 147 {
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 // Count number of contiguous 0 bits starting from the LSB.
 158 static int ctz(reg_t val)
 159 {
 160   int res = 0;
 161   if (val)
 162     while ((val & 1) == 0)
 163       val >>= 1, res++;
 164   return res;
 165 }
 166
 167 void processor_t::take_interrupt(reg_t pending_interrupts)
 168 {
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 171   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 172
 173   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 174   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 175   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   state.dcsr.cause = cause;
 193   state.dcsr.prv = state.prv;
 194   set_privilege(PRV_M);
 195   state.dpc = state.pc;
 196   state.pc = DEBUG_ROM_START;
 197 }
 198
 199 void processor_t::take_trap(trap_t& t, reg_t epc)
 200 {
 201   if (debug) {
 202     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 203             id, t.name(), epc);
 204     if (t.has_badaddr())
 205       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 206           t.get_badaddr());
 207   }
 208
 209   if (t.cause() == CAUSE_BREAKPOINT && (
 210               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 211               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 212               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 213               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 214     enter_debug_mode(DCSR_CAUSE_SWBP);
 215     return;
 216   }
 217
 218   if (state.dcsr.cause) {
 219     state.pc = DEBUG_ROM_EXCEPTION;
 220     return;
 221   }
 222
 223   // by default, trap to M-mode, unless delegated to S-mode
 224   reg_t bit = t.cause();
 225   reg_t deleg = state.medeleg;
 226   if (bit & ((reg_t)1 << (max_xlen-1)))
 227     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 228   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 229     // handle the trap in S-mode
 230     state.pc = state.stvec;
 231     state.scause = t.cause();
 232     state.sepc = epc;
 233     if (t.has_badaddr())
 234       state.sbadaddr = t.get_badaddr();
 235
 236     reg_t s = state.mstatus;
 237     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 238     s = set_field(s, MSTATUS_SPP, state.prv);
 239     s = set_field(s, MSTATUS_SIE, 0);
 240     set_csr(CSR_MSTATUS, s);
 241     set_privilege(PRV_S);
 242   } else {
 243     state.pc = state.mtvec;
 244     state.mepc = epc;
 245     state.mcause = t.cause();
 246     if (t.has_badaddr())
 247       state.mbadaddr = t.get_badaddr();
 248
 249     reg_t s = state.mstatus;
 250     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 251     s = set_field(s, MSTATUS_MPP, state.prv);
 252     s = set_field(s, MSTATUS_MIE, 0);
 253     set_csr(CSR_MSTATUS, s);
 254     set_privilege(PRV_M);
 255   }
 256
 257   yield_load_reservation();
 258 }
 259
 260 void processor_t::disasm(insn_t insn)
 261 {
 262   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 263   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 264           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 265 }
 266
 267 static bool validate_vm(int max_xlen, reg_t vm)
 268 {
 269   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 270     return true;
 271   if (max_xlen == 32 && vm == VM_SV32)
 272     return true;
 273   return vm == VM_MBARE;
 274 }
 275
 276 int processor_t::paddr_bits()
 277 {
 278   assert(xlen == max_xlen);
 279   return max_xlen == 64 ? 50 : 34;
 280 }
 281
 282 void processor_t::set_csr(int which, reg_t val)
 283 {
 284   val = zext_xlen(val);
 285   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 286   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 287   switch (which)
 288   {
 289     case CSR_FFLAGS:
 290       dirty_fp_state;
 291       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 292       break;
 293     case CSR_FRM:
 294       dirty_fp_state;
 295       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 296       break;
 297     case CSR_FCSR:
 298       dirty_fp_state;
 299       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 300       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 301       break;
 302     case CSR_MSTATUS: {
 303       if ((val ^ state.mstatus) &
 304           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 305         mmu->flush_tlb();
 306
 307       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 308                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 309                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 310
 311       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 312         mask |= MSTATUS_VM;
 313
 314       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 315
 316       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 317       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 318       if (max_xlen == 32)
 319         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 320       else
 321         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 322
 323       // spike supports the notion of xlen < max_xlen, but current priv spec
 324       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 325       xlen = max_xlen;
 326       break;
 327     }
 328     case CSR_MIP: {
 329       reg_t mask = MIP_SSIP | MIP_STIP;
 330       state.mip = (state.mip & ~mask) | (val & mask);
 331       break;
 332     }
 333     case CSR_MIE:
 334       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 335       break;
 336     case CSR_MIDELEG:
 337       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 338       break;
 339     case CSR_MEDELEG: {
 340       reg_t mask = 0;
 341 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 342 #include "encoding.h"
 343 #undef DECLARE_CAUSE
 344       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 345       break;
 346     }
 347     case CSR_MINSTRET:
 348     case CSR_MCYCLE:
 349       if (xlen == 32)
 350         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 351       else
 352         state.minstret = val;
 353       break;
 354     case CSR_MINSTRETH:
 355     case CSR_MCYCLEH:
 356       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 357       break;
 358     case CSR_MUCOUNTEREN:
 359       state.mucounteren = val;
 360       break;
 361     case CSR_MSCOUNTEREN:
 362       state.mscounteren = val;
 363       break;
 364     case CSR_SSTATUS: {
 365       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 366                  | SSTATUS_XS | SSTATUS_PUM;
 367       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 368     }
 369     case CSR_SIP: {
 370       reg_t mask = MIP_SSIP & state.mideleg;
 371       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 372     }
 373     case CSR_SIE:
 374       return set_csr(CSR_MIE,
 375                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 376     case CSR_SPTBR: {
 377       // upper bits of sptbr are the ASID; we only support ASID = 0
 378       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 379       break;
 380     }
 381     case CSR_SEPC: state.sepc = val; break;
 382     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 383     case CSR_SSCRATCH: state.sscratch = val; break;
 384     case CSR_SCAUSE: state.scause = val; break;
 385     case CSR_SBADADDR: state.sbadaddr = val; break;
 386     case CSR_MEPC: state.mepc = val; break;
 387     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 388     case CSR_MSCRATCH: state.mscratch = val; break;
 389     case CSR_MCAUSE: state.mcause = val; break;
 390     case CSR_MBADADDR: state.mbadaddr = val; break;
 391     case CSR_MISA: {
 392       if (!(val & (1L << ('F' - 'A'))))
 393         val &= ~(1L << ('D' - 'A'));
 394
 395       // allow MAFDC bits in MISA to be modified
 396       reg_t mask = 0;
 397       mask |= 1L << ('M' - 'A');
 398       mask |= 1L << ('A' - 'A');
 399       mask |= 1L << ('F' - 'A');
 400       mask |= 1L << ('D' - 'A');
 401       mask |= 1L << ('C' - 'A');
 402       mask &= max_isa;
 403
 404       isa = (val & mask) | (isa & ~mask);
 405       break;
 406     }
 407     case CSR_TSELECT:
 408       if (val < state.num_triggers) {
 409         state.tselect = val;
 410       }
 411       break;
 412     case CSR_TDATA1:
 413       {
 414         mcontrol_t *mc = &state.mcontrol[state.tselect];
 415         if (mc->dmode && !state.dcsr.cause) {
 416           break;
 417         }
 418         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 419         mc->select = get_field(val, MCONTROL_SELECT);
 420         mc->timing = get_field(val, MCONTROL_TIMING);
 421         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 422         mc->chain = get_field(val, MCONTROL_CHAIN);
 423         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 424         mc->m = get_field(val, MCONTROL_M);
 425         mc->h = get_field(val, MCONTROL_H);
 426         mc->s = get_field(val, MCONTROL_S);
 427         mc->u = get_field(val, MCONTROL_U);
 428         mc->execute = get_field(val, MCONTROL_EXECUTE);
 429         mc->store = get_field(val, MCONTROL_STORE);
 430         mc->load = get_field(val, MCONTROL_LOAD);
 431         // Assume we're here because of csrw.
 432         if (mc->execute)
 433           mc->timing = 0;
 434         trigger_updated();
 435       }
 436       break;
 437     case CSR_TDATA2:
 438       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 439         break;
 440       }
 441       if (state.tselect < state.num_triggers) {
 442         state.tdata2[state.tselect] = val;
 443       }
 444       break;
 445     case CSR_DCSR:
 446       state.dcsr.prv = get_field(val, DCSR_PRV);
 447       state.dcsr.step = get_field(val, DCSR_STEP);
 448       // TODO: ndreset and fullreset
 449       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 450       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 451       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 452       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 453       state.dcsr.halt = get_field(val, DCSR_HALT);
 454       break;
 455     case CSR_DPC:
 456       state.dpc = val;
 457       break;
 458     case CSR_DSCRATCH:
 459       state.dscratch = val;
 460       break;
 461   }
 462 }
 463
 464 reg_t processor_t::get_csr(int which)
 465 {
 466   reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
 467                  state.prv == PRV_S ? state.mscounteren : -1U;
 468   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 469
 470   if (ctr_ok) {
 471     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 472       return 0;
 473     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 474       return 0;
 475   }
 476   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 477     return 0;
 478   if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 479     return 0;
 480   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 481     return 0;
 482
 483   switch (which)
 484   {
 485     case CSR_FFLAGS:
 486       require_fp;
 487       if (!supports_extension('F'))
 488         break;
 489       return state.fflags;
 490     case CSR_FRM:
 491       require_fp;
 492       if (!supports_extension('F'))
 493         break;
 494       return state.frm;
 495     case CSR_FCSR:
 496       require_fp;
 497       if (!supports_extension('F'))
 498         break;
 499       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 500     case CSR_INSTRET:
 501     case CSR_CYCLE:
 502       if (ctr_ok)
 503         return state.minstret;
 504       break;
 505     case CSR_MINSTRET:
 506     case CSR_MCYCLE:
 507       return state.minstret;
 508     case CSR_MINSTRETH:
 509     case CSR_MCYCLEH:
 510       if (xlen == 32)
 511         return state.minstret >> 32;
 512       break;
 513     case CSR_MUCOUNTEREN: return state.mucounteren;
 514     case CSR_MSCOUNTEREN: return state.mscounteren;
 515     case CSR_SSTATUS: {
 516       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 517                  | SSTATUS_XS | SSTATUS_PUM;
 518       reg_t sstatus = state.mstatus & mask;
 519       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 520           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 521         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 522       return sstatus;
 523     }
 524     case CSR_SIP: return state.mip & state.mideleg;
 525     case CSR_SIE: return state.mie & state.mideleg;
 526     case CSR_SEPC: return state.sepc;
 527     case CSR_SBADADDR: return state.sbadaddr;
 528     case CSR_STVEC: return state.stvec;
 529     case CSR_SCAUSE:
 530       if (max_xlen > xlen)
 531         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 532       return state.scause;
 533     case CSR_SPTBR: return state.sptbr;
 534     case CSR_SSCRATCH: return state.sscratch;
 535     case CSR_MSTATUS: return state.mstatus;
 536     case CSR_MIP: return state.mip;
 537     case CSR_MIE: return state.mie;
 538     case CSR_MEPC: return state.mepc;
 539     case CSR_MSCRATCH: return state.mscratch;
 540     case CSR_MCAUSE: return state.mcause;
 541     case CSR_MBADADDR: return state.mbadaddr;
 542     case CSR_MISA: return isa;
 543     case CSR_MARCHID: return 0;
 544     case CSR_MIMPID: return 0;
 545     case CSR_MVENDORID: return 0;
 546     case CSR_MHARTID: return id;
 547     case CSR_MTVEC: return state.mtvec;
 548     case CSR_MEDELEG: return state.medeleg;
 549     case CSR_MIDELEG: return state.mideleg;
 550     case CSR_TSELECT: return state.tselect;
 551     case CSR_TDATA1:
 552       if (state.tselect < state.num_triggers) {
 553         reg_t v = 0;
 554         mcontrol_t *mc = &state.mcontrol[state.tselect];
 555         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 556         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 557         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 558         v = set_field(v, MCONTROL_SELECT, mc->select);
 559         v = set_field(v, MCONTROL_TIMING, mc->timing);
 560         v = set_field(v, MCONTROL_ACTION, mc->action);
 561         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 562         v = set_field(v, MCONTROL_MATCH, mc->match);
 563         v = set_field(v, MCONTROL_M, mc->m);
 564         v = set_field(v, MCONTROL_H, mc->h);
 565         v = set_field(v, MCONTROL_S, mc->s);
 566         v = set_field(v, MCONTROL_U, mc->u);
 567         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 568         v = set_field(v, MCONTROL_STORE, mc->store);
 569         v = set_field(v, MCONTROL_LOAD, mc->load);
 570         return v;
 571       } else {
 572         return 0;
 573       }
 574       break;
 575     case CSR_TDATA2:
 576       if (state.tselect < state.num_triggers) {
 577         return state.tdata2[state.tselect];
 578       } else {
 579         return 0;
 580       }
 581       break;
 582     case CSR_TDATA3: return 0;
 583     case CSR_DCSR:
 584       {
 585         uint32_t v = 0;
 586         v = set_field(v, DCSR_XDEBUGVER, 1);
 587         v = set_field(v, DCSR_NDRESET, 0);
 588         v = set_field(v, DCSR_FULLRESET, 0);
 589         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 590         v = set_field(v, DCSR_STEP, state.dcsr.step);
 591         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 592         v = set_field(v, DCSR_STOPCYCLE, 0);
 593         v = set_field(v, DCSR_STOPTIME, 0);
 594         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 595         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 596         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 597         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 598         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 599         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 600         return v;
 601       }
 602     case CSR_DPC:
 603       return state.dpc;
 604     case CSR_DSCRATCH:
 605       return state.dscratch;
 606   }
 607   throw trap_illegal_instruction();
 608 }
 609
 610 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 611 {
 612   throw trap_illegal_instruction();
 613 }
 614
 615 insn_func_t processor_t::decode_insn(insn_t insn)
 616 {
 617   // look up opcode in hash table
 618   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 619   insn_desc_t desc = opcode_cache[idx];
 620
 621   if (unlikely(insn.bits() != desc.match)) {
 622     // fall back to linear search
 623     insn_desc_t* p = &instructions[0];
 624     while ((insn.bits() & p->mask) != p->match)
 625       p++;
 626     desc = *p;
 627
 628     if (p->mask != 0 && p > &instructions[0]) {
 629       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 630         // move to front of opcode list to reduce miss penalty
 631         while (--p >= &instructions[0])
 632           *(p+1) = *p;
 633         instructions[0] = desc;
 634       }
 635     }
 636
 637     opcode_cache[idx] = desc;
 638     opcode_cache[idx].match = insn.bits();
 639   }
 640
 641   return xlen == 64 ? desc.rv64 : desc.rv32;
 642 }
 643
 644 void processor_t::register_insn(insn_desc_t desc)
 645 {
 646   instructions.push_back(desc);
 647 }
 648
 649 void processor_t::build_opcode_map()
 650 {
 651   struct cmp {
 652     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 653       if (lhs.match == rhs.match)
 654         return lhs.mask > rhs.mask;
 655       return lhs.match > rhs.match;
 656     }
 657   };
 658   std::sort(instructions.begin(), instructions.end(), cmp());
 659
 660   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 661     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 662 }
 663
 664 void processor_t::register_extension(extension_t* x)
 665 {
 666   for (auto insn : x->get_instructions())
 667     register_insn(insn);
 668   build_opcode_map();
 669   for (auto disasm_insn : x->get_disasms())
 670     disassembler->add_insn(disasm_insn);
 671   if (ext != NULL)
 672     throw std::logic_error("only one extension may be registered");
 673   ext = x;
 674   x->set_processor(this);
 675 }
 676
 677 void processor_t::register_base_instructions()
 678 {
 679   #define DECLARE_INSN(name, match, mask) \
 680     insn_bits_t name##_match = (match), name##_mask = (mask);
 681   #include "encoding.h"
 682   #undef DECLARE_INSN
 683
 684   #define DEFINE_INSN(name) \
 685     REGISTER_INSN(this, name, name##_match, name##_mask)
 686   #include "insn_list.h"
 687   #undef DEFINE_INSN
 688
 689   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 690   build_opcode_map();
 691 }
 692
 693 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 694 {
 695   return false;
 696 }
 697
 698 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 699 {
 700   switch (addr)
 701   {
 702     case 0:
 703       state.mip &= ~MIP_MSIP;
 704       if (bytes[0] & 1)
 705         state.mip |= MIP_MSIP;
 706       return true;
 707
 708     default:
 709       return false;
 710   }
 711 }
 712
 713 void processor_t::trigger_updated()
 714 {
 715   mmu->flush_tlb();
 716   mmu->check_triggers_fetch = false;
 717   mmu->check_triggers_load = false;
 718   mmu->check_triggers_store = false;
 719
 720   for (unsigned i = 0; i < state.num_triggers; i++) {
 721     if (state.mcontrol[i].execute) {
 722       mmu->check_triggers_fetch = true;
 723     }
 724     if (state.mcontrol[i].load) {
 725       mmu->check_triggers_load = true;
 726     }
 727     if (state.mcontrol[i].store) {
 728       mmu->check_triggers_store = true;
 729     }
 730   }
 731 }