riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112 }
 113
 114 void state_t::reset()
 115 {
 116   memset(this, 0, sizeof(*this));
 117   prv = PRV_M;
 118   pc = DEFAULT_RSTVEC;
 119   mtvec = DEFAULT_MTVEC;
 120   load_reservation = -1;
 121   tselect = 0;
 122   for (unsigned int i = 0; i < num_triggers; i++)
 123     mcontrol[i].type = 2;
 124 }
 125
 126 void processor_t::set_debug(bool value)
 127 {
 128   debug = value;
 129   if (ext)
 130     ext->set_debug(value);
 131 }
 132
 133 void processor_t::set_histogram(bool value)
 134 {
 135   histogram_enabled = value;
 136 #ifndef RISCV_ENABLE_HISTOGRAM
 137   if (value) {
 138     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 139     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 140   }
 141 #endif
 142 }
 143
 144 void processor_t::reset()
 145 {
 146   state.reset();
 147   state.dcsr.halt = halt_on_reset;
 148   halt_on_reset = false;
 149   set_csr(CSR_MSTATUS, state.mstatus);
 150
 151   if (ext)
 152     ext->reset(); // reset the extension
 153 }
 154
 155 void processor_t::raise_interrupt(reg_t which)
 156 {
 157   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 158 }
 159
 160 // Count number of contiguous 0 bits starting from the LSB.
 161 static int ctz(reg_t val)
 162 {
 163   int res = 0;
 164   if (val)
 165     while ((val & 1) == 0)
 166       val >>= 1, res++;
 167   return res;
 168 }
 169
 170 void processor_t::take_interrupt()
 171 {
 172   reg_t pending_interrupts = state.mip & state.mie;
 173
 174   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 175   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 176   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 177
 178   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 179   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 180   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 181
 182   if (enabled_interrupts)
 183     raise_interrupt(ctz(enabled_interrupts));
 184 }
 185
 186 void processor_t::set_privilege(reg_t prv)
 187 {
 188   assert(prv <= PRV_M);
 189   if (prv == PRV_H)
 190     prv = PRV_U;
 191   mmu->flush_tlb();
 192   state.prv = prv;
 193 }
 194
 195 void processor_t::enter_debug_mode(uint8_t cause)
 196 {
 197   state.dcsr.cause = cause;
 198   state.dcsr.prv = state.prv;
 199   set_privilege(PRV_M);
 200   state.dpc = state.pc;
 201   state.pc = DEBUG_ROM_START;
 202 }
 203
 204 void processor_t::take_trap(trap_t& t, reg_t epc)
 205 {
 206   if (debug) {
 207     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 208             id, t.name(), epc);
 209     if (t.has_badaddr())
 210       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 211           t.get_badaddr());
 212   }
 213
 214   if (t.cause() == CAUSE_BREAKPOINT && (
 215               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 216               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 217               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 218               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 219     enter_debug_mode(DCSR_CAUSE_SWBP);
 220     return;
 221   }
 222
 223   if (state.dcsr.cause) {
 224     state.pc = DEBUG_ROM_EXCEPTION;
 225     return;
 226   }
 227
 228   // by default, trap to M-mode, unless delegated to S-mode
 229   reg_t bit = t.cause();
 230   reg_t deleg = state.medeleg;
 231   if (bit & ((reg_t)1 << (max_xlen-1)))
 232     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 233   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 234     // handle the trap in S-mode
 235     state.pc = state.stvec;
 236     state.scause = t.cause();
 237     state.sepc = epc;
 238     if (t.has_badaddr())
 239       state.sbadaddr = t.get_badaddr();
 240
 241     reg_t s = state.mstatus;
 242     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 243     s = set_field(s, MSTATUS_SPP, state.prv);
 244     s = set_field(s, MSTATUS_SIE, 0);
 245     set_csr(CSR_MSTATUS, s);
 246     set_privilege(PRV_S);
 247   } else {
 248     state.pc = state.mtvec;
 249     state.mepc = epc;
 250     state.mcause = t.cause();
 251     if (t.has_badaddr())
 252       state.mbadaddr = t.get_badaddr();
 253
 254     reg_t s = state.mstatus;
 255     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 256     s = set_field(s, MSTATUS_MPP, state.prv);
 257     s = set_field(s, MSTATUS_MIE, 0);
 258     set_csr(CSR_MSTATUS, s);
 259     set_privilege(PRV_M);
 260   }
 261
 262   yield_load_reservation();
 263 }
 264
 265 void processor_t::disasm(insn_t insn)
 266 {
 267   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 268   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 269           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 270 }
 271
 272 static bool validate_vm(int max_xlen, reg_t vm)
 273 {
 274   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 275     return true;
 276   if (max_xlen == 32 && vm == VM_SV32)
 277     return true;
 278   return vm == VM_MBARE;
 279 }
 280
 281 int processor_t::paddr_bits()
 282 {
 283   assert(xlen == max_xlen);
 284   return max_xlen == 64 ? 50 : 34;
 285 }
 286
 287 void processor_t::set_csr(int which, reg_t val)
 288 {
 289   val = zext_xlen(val);
 290   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 291   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 292   switch (which)
 293   {
 294     case CSR_FFLAGS:
 295       dirty_fp_state;
 296       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 297       break;
 298     case CSR_FRM:
 299       dirty_fp_state;
 300       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 301       break;
 302     case CSR_FCSR:
 303       dirty_fp_state;
 304       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 305       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 306       break;
 307     case CSR_MSTATUS: {
 308       if ((val ^ state.mstatus) &
 309           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 310         mmu->flush_tlb();
 311
 312       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 313                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 314                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 315
 316       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 317         mask |= MSTATUS_VM;
 318
 319       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 320
 321       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 322       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 323       if (max_xlen == 32)
 324         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 325       else
 326         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 327
 328       // spike supports the notion of xlen < max_xlen, but current priv spec
 329       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 330       xlen = max_xlen;
 331       break;
 332     }
 333     case CSR_MIP: {
 334       reg_t mask = MIP_SSIP | MIP_STIP;
 335       state.mip = (state.mip & ~mask) | (val & mask);
 336       break;
 337     }
 338     case CSR_MIE:
 339       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 340       break;
 341     case CSR_MIDELEG:
 342       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 343       break;
 344     case CSR_MEDELEG: {
 345       reg_t mask = 0;
 346 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 347 #include "encoding.h"
 348 #undef DECLARE_CAUSE
 349       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 350       break;
 351     }
 352     case CSR_MUCOUNTEREN:
 353       state.mucounteren = val & 7;
 354       break;
 355     case CSR_MSCOUNTEREN:
 356       state.mscounteren = val & 7;
 357       break;
 358     case CSR_SSTATUS: {
 359       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 360                  | SSTATUS_XS | SSTATUS_PUM;
 361       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 362     }
 363     case CSR_SIP:
 364       return set_csr(CSR_MIP,
 365                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 366     case CSR_SIE:
 367       return set_csr(CSR_MIE,
 368                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 369     case CSR_SPTBR: {
 370       // upper bits of sptbr are the ASID; we only support ASID = 0
 371       state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
 372       break;
 373     }
 374     case CSR_SEPC: state.sepc = val; break;
 375     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 376     case CSR_SSCRATCH: state.sscratch = val; break;
 377     case CSR_SCAUSE: state.scause = val; break;
 378     case CSR_SBADADDR: state.sbadaddr = val; break;
 379     case CSR_MEPC: state.mepc = val; break;
 380     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 381     case CSR_MSCRATCH: state.mscratch = val; break;
 382     case CSR_MCAUSE: state.mcause = val; break;
 383     case CSR_MBADADDR: state.mbadaddr = val; break;
 384     case CSR_TSELECT:
 385       if (val < state.num_triggers) {
 386         state.tselect = val;
 387       }
 388       break;
 389     case CSR_TDATA1:
 390       {
 391         mcontrol_t *mc = &state.mcontrol[state.tselect];
 392         if (mc->dmode && !state.dcsr.cause) {
 393           throw trap_illegal_instruction();
 394         }
 395         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 396         mc->select = get_field(val, MCONTROL_SELECT);
 397         mc->timing = get_field(val, MCONTROL_TIMING);
 398         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 399         mc->chain = get_field(val, MCONTROL_CHAIN);
 400         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 401         mc->m = get_field(val, MCONTROL_M);
 402         mc->h = get_field(val, MCONTROL_H);
 403         mc->s = get_field(val, MCONTROL_S);
 404         mc->u = get_field(val, MCONTROL_U);
 405         mc->execute = get_field(val, MCONTROL_EXECUTE);
 406         mc->store = get_field(val, MCONTROL_STORE);
 407         mc->load = get_field(val, MCONTROL_LOAD);
 408         // Assume we're here because of csrw.
 409         if (mc->execute)
 410           mc->timing = 0;
 411         if (mc->load)
 412           mc->timing = 1;
 413         trigger_updated();
 414       }
 415       break;
 416     case CSR_TDATA2:
 417       if (state.tselect < state.num_triggers) {
 418         state.tdata2[state.tselect] = val;
 419       }
 420       break;
 421     case CSR_DCSR:
 422       state.dcsr.prv = get_field(val, DCSR_PRV);
 423       state.dcsr.step = get_field(val, DCSR_STEP);
 424       // TODO: ndreset and fullreset
 425       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 426       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 427       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 428       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 429       state.dcsr.halt = get_field(val, DCSR_HALT);
 430       break;
 431     case CSR_DPC:
 432       state.dpc = val;
 433       break;
 434     case CSR_DSCRATCH:
 435       state.dscratch = val;
 436       break;
 437   }
 438 }
 439
 440 reg_t processor_t::get_csr(int which)
 441 {
 442   switch (which)
 443   {
 444     case CSR_FFLAGS:
 445       require_fp;
 446       if (!supports_extension('F'))
 447         break;
 448       return state.fflags;
 449     case CSR_FRM:
 450       require_fp;
 451       if (!supports_extension('F'))
 452         break;
 453       return state.frm;
 454     case CSR_FCSR:
 455       require_fp;
 456       if (!supports_extension('F'))
 457         break;
 458       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 459     case CSR_TIME:
 460     case CSR_INSTRET:
 461     case CSR_CYCLE:
 462       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 463         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 464       break;
 465     case CSR_STIME:
 466     case CSR_SINSTRET:
 467     case CSR_SCYCLE:
 468       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 469         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 470       break;
 471     case CSR_MUCOUNTEREN: return state.mucounteren;
 472     case CSR_MSCOUNTEREN: return state.mscounteren;
 473     case CSR_MUCYCLE_DELTA: return 0;
 474     case CSR_MUTIME_DELTA: return 0;
 475     case CSR_MUINSTRET_DELTA: return 0;
 476     case CSR_MSCYCLE_DELTA: return 0;
 477     case CSR_MSTIME_DELTA: return 0;
 478     case CSR_MSINSTRET_DELTA: return 0;
 479     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 480     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 481     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 482     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 483     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 484     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 485     case CSR_MCYCLE: return state.minstret;
 486     case CSR_MINSTRET: return state.minstret;
 487     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 488     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 489     case CSR_SSTATUS: {
 490       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 491                  | SSTATUS_XS | SSTATUS_PUM;
 492       reg_t sstatus = state.mstatus & mask;
 493       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 494           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 495         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 496       return sstatus;
 497     }
 498     case CSR_SIP: return state.mip & state.mideleg;
 499     case CSR_SIE: return state.mie & state.mideleg;
 500     case CSR_SEPC: return state.sepc;
 501     case CSR_SBADADDR: return state.sbadaddr;
 502     case CSR_STVEC: return state.stvec;
 503     case CSR_SCAUSE:
 504       if (max_xlen > xlen)
 505         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 506       return state.scause;
 507     case CSR_SPTBR: return state.sptbr;
 508     case CSR_SSCRATCH: return state.sscratch;
 509     case CSR_MSTATUS: return state.mstatus;
 510     case CSR_MIP: return state.mip;
 511     case CSR_MIE: return state.mie;
 512     case CSR_MEPC: return state.mepc;
 513     case CSR_MSCRATCH: return state.mscratch;
 514     case CSR_MCAUSE: return state.mcause;
 515     case CSR_MBADADDR: return state.mbadaddr;
 516     case CSR_MISA: return isa;
 517     case CSR_MARCHID: return 0;
 518     case CSR_MIMPID: return 0;
 519     case CSR_MVENDORID: return 0;
 520     case CSR_MHARTID: return id;
 521     case CSR_MTVEC: return state.mtvec;
 522     case CSR_MEDELEG: return state.medeleg;
 523     case CSR_MIDELEG: return state.mideleg;
 524     case CSR_TSELECT: return state.tselect;
 525     case CSR_TDATA1:
 526       if (state.tselect < state.num_triggers) {
 527         reg_t v = 0;
 528         mcontrol_t *mc = &state.mcontrol[state.tselect];
 529         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 530         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 531         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 532         v = set_field(v, MCONTROL_SELECT, mc->select);
 533         v = set_field(v, MCONTROL_TIMING, mc->timing);
 534         v = set_field(v, MCONTROL_ACTION, mc->action);
 535         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 536         v = set_field(v, MCONTROL_MATCH, mc->match);
 537         v = set_field(v, MCONTROL_M, mc->m);
 538         v = set_field(v, MCONTROL_H, mc->h);
 539         v = set_field(v, MCONTROL_S, mc->s);
 540         v = set_field(v, MCONTROL_U, mc->u);
 541         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 542         v = set_field(v, MCONTROL_STORE, mc->store);
 543         v = set_field(v, MCONTROL_LOAD, mc->load);
 544         return v;
 545       } else {
 546         return 0;
 547       }
 548       break;
 549     case CSR_TDATA2:
 550       if (state.tselect < state.num_triggers) {
 551         return state.tdata2[state.tselect];
 552       } else {
 553         return 0;
 554       }
 555       break;
 556     case CSR_DCSR:
 557       {
 558         uint32_t v = 0;
 559         v = set_field(v, DCSR_XDEBUGVER, 1);
 560         v = set_field(v, DCSR_NDRESET, 0);
 561         v = set_field(v, DCSR_FULLRESET, 0);
 562         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 563         v = set_field(v, DCSR_STEP, state.dcsr.step);
 564         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 565         v = set_field(v, DCSR_STOPCYCLE, 0);
 566         v = set_field(v, DCSR_STOPTIME, 0);
 567         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 568         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 569         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 570         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 571         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 572         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 573         return v;
 574       }
 575     case CSR_DPC:
 576       return state.dpc;
 577     case CSR_DSCRATCH:
 578       return state.dscratch;
 579   }
 580   throw trap_illegal_instruction();
 581 }
 582
 583 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 584 {
 585   throw trap_illegal_instruction();
 586 }
 587
 588 insn_func_t processor_t::decode_insn(insn_t insn)
 589 {
 590   // look up opcode in hash table
 591   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 592   insn_desc_t desc = opcode_cache[idx];
 593
 594   if (unlikely(insn.bits() != desc.match)) {
 595     // fall back to linear search
 596     insn_desc_t* p = &instructions[0];
 597     while ((insn.bits() & p->mask) != p->match)
 598       p++;
 599     desc = *p;
 600
 601     if (p->mask != 0 && p > &instructions[0]) {
 602       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 603         // move to front of opcode list to reduce miss penalty
 604         while (--p >= &instructions[0])
 605           *(p+1) = *p;
 606         instructions[0] = desc;
 607       }
 608     }
 609
 610     opcode_cache[idx] = desc;
 611     opcode_cache[idx].match = insn.bits();
 612   }
 613
 614   return xlen == 64 ? desc.rv64 : desc.rv32;
 615 }
 616
 617 void processor_t::register_insn(insn_desc_t desc)
 618 {
 619   instructions.push_back(desc);
 620 }
 621
 622 void processor_t::build_opcode_map()
 623 {
 624   struct cmp {
 625     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 626       if (lhs.match == rhs.match)
 627         return lhs.mask > rhs.mask;
 628       return lhs.match > rhs.match;
 629     }
 630   };
 631   std::sort(instructions.begin(), instructions.end(), cmp());
 632
 633   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 634     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 635 }
 636
 637 void processor_t::register_extension(extension_t* x)
 638 {
 639   for (auto insn : x->get_instructions())
 640     register_insn(insn);
 641   build_opcode_map();
 642   for (auto disasm_insn : x->get_disasms())
 643     disassembler->add_insn(disasm_insn);
 644   if (ext != NULL)
 645     throw std::logic_error("only one extension may be registered");
 646   ext = x;
 647   x->set_processor(this);
 648 }
 649
 650 void processor_t::register_base_instructions()
 651 {
 652   #define DECLARE_INSN(name, match, mask) \
 653     insn_bits_t name##_match = (match), name##_mask = (mask);
 654   #include "encoding.h"
 655   #undef DECLARE_INSN
 656
 657   #define DEFINE_INSN(name) \
 658     REGISTER_INSN(this, name, name##_match, name##_mask)
 659   #include "insn_list.h"
 660   #undef DEFINE_INSN
 661
 662   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 663   build_opcode_map();
 664 }
 665
 666 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 667 {
 668   return false;
 669 }
 670
 671 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 672 {
 673   switch (addr)
 674   {
 675     case 0:
 676       state.mip &= ~MIP_MSIP;
 677       if (bytes[0] & 1)
 678         state.mip |= MIP_MSIP;
 679       return true;
 680
 681     default:
 682       return false;
 683   }
 684 }
 685
 686 void processor_t::trigger_updated()
 687 {
 688   mmu->flush_tlb();
 689   mmu->check_triggers_fetch = false;
 690   mmu->check_triggers_load = false;
 691   mmu->check_triggers_store = false;
 692
 693   for (unsigned i = 0; i < state.num_triggers; i++) {
 694     if (state.mcontrol[i].execute) {
 695       mmu->check_triggers_fetch = true;
 696     }
 697     if (state.mcontrol[i].load) {
 698       mmu->check_triggers_load = true;
 699     }
 700     if (state.mcontrol[i].store) {
 701       mmu->check_triggers_store = true;
 702     }
 703   }
 704 }