riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   mtvec = DEFAULT_MTVEC;
 122   load_reservation = -1;
 123   tselect = 0;
 124   for (unsigned int i = 0; i < num_triggers; i++)
 125     mcontrol[i].type = 2;
 126 }
 127
 128 void processor_t::set_debug(bool value)
 129 {
 130   debug = value;
 131   if (ext)
 132     ext->set_debug(value);
 133 }
 134
 135 void processor_t::set_histogram(bool value)
 136 {
 137   histogram_enabled = value;
 138 #ifndef RISCV_ENABLE_HISTOGRAM
 139   if (value) {
 140     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 141     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 142   }
 143 #endif
 144 }
 145
 146 void processor_t::reset()
 147 {
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 // Count number of contiguous 0 bits starting from the LSB.
 158 static int ctz(reg_t val)
 159 {
 160   int res = 0;
 161   if (val)
 162     while ((val & 1) == 0)
 163       val >>= 1, res++;
 164   return res;
 165 }
 166
 167 void processor_t::take_interrupt(reg_t pending_interrupts)
 168 {
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 171   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 172
 173   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 174   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 175   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 176
 177   if (enabled_interrupts)
 178     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 179 }
 180
 181 void processor_t::set_privilege(reg_t prv)
 182 {
 183   assert(prv <= PRV_M);
 184   if (prv == PRV_H)
 185     prv = PRV_U;
 186   mmu->flush_tlb();
 187   state.prv = prv;
 188 }
 189
 190 void processor_t::enter_debug_mode(uint8_t cause)
 191 {
 192   state.dcsr.cause = cause;
 193   state.dcsr.prv = state.prv;
 194   set_privilege(PRV_M);
 195   state.dpc = state.pc;
 196   state.pc = DEBUG_ROM_START;
 197 }
 198
 199 void processor_t::take_trap(trap_t& t, reg_t epc)
 200 {
 201   if (debug) {
 202     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 203             id, t.name(), epc);
 204     if (t.has_badaddr())
 205       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 206           t.get_badaddr());
 207   }
 208
 209   if (t.cause() == CAUSE_BREAKPOINT && (
 210               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 211               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 212               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 213               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 214     enter_debug_mode(DCSR_CAUSE_SWBP);
 215     return;
 216   }
 217
 218   if (state.dcsr.cause) {
 219     state.pc = DEBUG_ROM_EXCEPTION;
 220     return;
 221   }
 222
 223   // by default, trap to M-mode, unless delegated to S-mode
 224   reg_t bit = t.cause();
 225   reg_t deleg = state.medeleg;
 226   if (bit & ((reg_t)1 << (max_xlen-1)))
 227     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 228   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 229     // handle the trap in S-mode
 230     state.pc = state.stvec;
 231     state.scause = t.cause();
 232     state.sepc = epc;
 233     if (t.has_badaddr())
 234       state.sbadaddr = t.get_badaddr();
 235
 236     reg_t s = state.mstatus;
 237     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 238     s = set_field(s, MSTATUS_SPP, state.prv);
 239     s = set_field(s, MSTATUS_SIE, 0);
 240     set_csr(CSR_MSTATUS, s);
 241     set_privilege(PRV_S);
 242   } else {
 243     state.pc = state.mtvec;
 244     state.mepc = epc;
 245     state.mcause = t.cause();
 246     if (t.has_badaddr())
 247       state.mbadaddr = t.get_badaddr();
 248
 249     reg_t s = state.mstatus;
 250     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 251     s = set_field(s, MSTATUS_MPP, state.prv);
 252     s = set_field(s, MSTATUS_MIE, 0);
 253     set_csr(CSR_MSTATUS, s);
 254     set_privilege(PRV_M);
 255   }
 256
 257   yield_load_reservation();
 258 }
 259
 260 void processor_t::disasm(insn_t insn)
 261 {
 262   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 263   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 264           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 265 }
 266
 267 int processor_t::paddr_bits()
 268 {
 269   assert(xlen == max_xlen);
 270   return max_xlen == 64 ? 50 : 34;
 271 }
 272
 273 void processor_t::set_csr(int which, reg_t val)
 274 {
 275   val = zext_xlen(val);
 276   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 277   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 278   switch (which)
 279   {
 280     case CSR_FFLAGS:
 281       dirty_fp_state;
 282       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 283       break;
 284     case CSR_FRM:
 285       dirty_fp_state;
 286       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 287       break;
 288     case CSR_FCSR:
 289       dirty_fp_state;
 290       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 291       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 292       break;
 293     case CSR_MSTATUS: {
 294       if ((val ^ state.mstatus) &
 295           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 296         mmu->flush_tlb();
 297
 298       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 299                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 300                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 301
 302       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 303
 304       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 305       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 306       if (max_xlen == 32)
 307         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 308       else
 309         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 310
 311       // spike supports the notion of xlen < max_xlen, but current priv spec
 312       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 313       xlen = max_xlen;
 314       break;
 315     }
 316     case CSR_MIP: {
 317       reg_t mask = MIP_SSIP | MIP_STIP;
 318       state.mip = (state.mip & ~mask) | (val & mask);
 319       break;
 320     }
 321     case CSR_MIE:
 322       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 323       break;
 324     case CSR_MIDELEG:
 325       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 326       break;
 327     case CSR_MEDELEG: {
 328       reg_t mask = 0;
 329 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 330 #include "encoding.h"
 331 #undef DECLARE_CAUSE
 332       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 333       break;
 334     }
 335     case CSR_MINSTRET:
 336     case CSR_MCYCLE:
 337       if (xlen == 32)
 338         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 339       else
 340         state.minstret = val;
 341       break;
 342     case CSR_MINSTRETH:
 343     case CSR_MCYCLEH:
 344       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 345       break;
 346     case CSR_MUCOUNTEREN:
 347       state.mucounteren = val;
 348       break;
 349     case CSR_MSCOUNTEREN:
 350       state.mscounteren = val;
 351       break;
 352     case CSR_SSTATUS: {
 353       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 354                  | SSTATUS_XS | SSTATUS_PUM;
 355       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 356     }
 357     case CSR_SIP: {
 358       reg_t mask = MIP_SSIP & state.mideleg;
 359       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 360     }
 361     case CSR_SIE:
 362       return set_csr(CSR_MIE,
 363                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 364     case CSR_SPTBR: {
 365       mmu->flush_tlb();
 366       if (max_xlen == 32)
 367         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 368       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 369                              get_field(val, SPTBR64_MODE) >= SPTBR_MODE_SV39))
 370         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 371       break;
 372     }
 373     case CSR_SEPC: state.sepc = val; break;
 374     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 375     case CSR_SSCRATCH: state.sscratch = val; break;
 376     case CSR_SCAUSE: state.scause = val; break;
 377     case CSR_SBADADDR: state.sbadaddr = val; break;
 378     case CSR_MEPC: state.mepc = val; break;
 379     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 380     case CSR_MSCRATCH: state.mscratch = val; break;
 381     case CSR_MCAUSE: state.mcause = val; break;
 382     case CSR_MBADADDR: state.mbadaddr = val; break;
 383     case CSR_MISA: {
 384       if (!(val & (1L << ('F' - 'A'))))
 385         val &= ~(1L << ('D' - 'A'));
 386
 387       // allow MAFDC bits in MISA to be modified
 388       reg_t mask = 0;
 389       mask |= 1L << ('M' - 'A');
 390       mask |= 1L << ('A' - 'A');
 391       mask |= 1L << ('F' - 'A');
 392       mask |= 1L << ('D' - 'A');
 393       mask |= 1L << ('C' - 'A');
 394       mask &= max_isa;
 395
 396       isa = (val & mask) | (isa & ~mask);
 397       break;
 398     }
 399     case CSR_TSELECT:
 400       if (val < state.num_triggers) {
 401         state.tselect = val;
 402       }
 403       break;
 404     case CSR_TDATA1:
 405       {
 406         mcontrol_t *mc = &state.mcontrol[state.tselect];
 407         if (mc->dmode && !state.dcsr.cause) {
 408           break;
 409         }
 410         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 411         mc->select = get_field(val, MCONTROL_SELECT);
 412         mc->timing = get_field(val, MCONTROL_TIMING);
 413         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 414         mc->chain = get_field(val, MCONTROL_CHAIN);
 415         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 416         mc->m = get_field(val, MCONTROL_M);
 417         mc->h = get_field(val, MCONTROL_H);
 418         mc->s = get_field(val, MCONTROL_S);
 419         mc->u = get_field(val, MCONTROL_U);
 420         mc->execute = get_field(val, MCONTROL_EXECUTE);
 421         mc->store = get_field(val, MCONTROL_STORE);
 422         mc->load = get_field(val, MCONTROL_LOAD);
 423         // Assume we're here because of csrw.
 424         if (mc->execute)
 425           mc->timing = 0;
 426         trigger_updated();
 427       }
 428       break;
 429     case CSR_TDATA2:
 430       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 431         break;
 432       }
 433       if (state.tselect < state.num_triggers) {
 434         state.tdata2[state.tselect] = val;
 435       }
 436       break;
 437     case CSR_DCSR:
 438       state.dcsr.prv = get_field(val, DCSR_PRV);
 439       state.dcsr.step = get_field(val, DCSR_STEP);
 440       // TODO: ndreset and fullreset
 441       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 442       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 443       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 444       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 445       state.dcsr.halt = get_field(val, DCSR_HALT);
 446       break;
 447     case CSR_DPC:
 448       state.dpc = val;
 449       break;
 450     case CSR_DSCRATCH:
 451       state.dscratch = val;
 452       break;
 453   }
 454 }
 455
 456 reg_t processor_t::get_csr(int which)
 457 {
 458   reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
 459                  state.prv == PRV_S ? state.mscounteren : -1U;
 460   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 461
 462   if (ctr_ok) {
 463     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 464       return 0;
 465     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 466       return 0;
 467   }
 468   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 469     return 0;
 470   if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 471     return 0;
 472   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 473     return 0;
 474
 475   switch (which)
 476   {
 477     case CSR_FFLAGS:
 478       require_fp;
 479       if (!supports_extension('F'))
 480         break;
 481       return state.fflags;
 482     case CSR_FRM:
 483       require_fp;
 484       if (!supports_extension('F'))
 485         break;
 486       return state.frm;
 487     case CSR_FCSR:
 488       require_fp;
 489       if (!supports_extension('F'))
 490         break;
 491       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 492     case CSR_INSTRET:
 493     case CSR_CYCLE:
 494       if (ctr_ok)
 495         return state.minstret;
 496       break;
 497     case CSR_MINSTRET:
 498     case CSR_MCYCLE:
 499       return state.minstret;
 500     case CSR_MINSTRETH:
 501     case CSR_MCYCLEH:
 502       if (xlen == 32)
 503         return state.minstret >> 32;
 504       break;
 505     case CSR_MUCOUNTEREN: return state.mucounteren;
 506     case CSR_MSCOUNTEREN: return state.mscounteren;
 507     case CSR_SSTATUS: {
 508       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 509                  | SSTATUS_XS | SSTATUS_PUM;
 510       reg_t sstatus = state.mstatus & mask;
 511       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 512           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 513         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 514       return sstatus;
 515     }
 516     case CSR_SIP: return state.mip & state.mideleg;
 517     case CSR_SIE: return state.mie & state.mideleg;
 518     case CSR_SEPC: return state.sepc;
 519     case CSR_SBADADDR: return state.sbadaddr;
 520     case CSR_STVEC: return state.stvec;
 521     case CSR_SCAUSE:
 522       if (max_xlen > xlen)
 523         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 524       return state.scause;
 525     case CSR_SPTBR: return state.sptbr;
 526     case CSR_SSCRATCH: return state.sscratch;
 527     case CSR_MSTATUS: return state.mstatus;
 528     case CSR_MIP: return state.mip;
 529     case CSR_MIE: return state.mie;
 530     case CSR_MEPC: return state.mepc;
 531     case CSR_MSCRATCH: return state.mscratch;
 532     case CSR_MCAUSE: return state.mcause;
 533     case CSR_MBADADDR: return state.mbadaddr;
 534     case CSR_MISA: return isa;
 535     case CSR_MARCHID: return 0;
 536     case CSR_MIMPID: return 0;
 537     case CSR_MVENDORID: return 0;
 538     case CSR_MHARTID: return id;
 539     case CSR_MTVEC: return state.mtvec;
 540     case CSR_MEDELEG: return state.medeleg;
 541     case CSR_MIDELEG: return state.mideleg;
 542     case CSR_TSELECT: return state.tselect;
 543     case CSR_TDATA1:
 544       if (state.tselect < state.num_triggers) {
 545         reg_t v = 0;
 546         mcontrol_t *mc = &state.mcontrol[state.tselect];
 547         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 548         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 549         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 550         v = set_field(v, MCONTROL_SELECT, mc->select);
 551         v = set_field(v, MCONTROL_TIMING, mc->timing);
 552         v = set_field(v, MCONTROL_ACTION, mc->action);
 553         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 554         v = set_field(v, MCONTROL_MATCH, mc->match);
 555         v = set_field(v, MCONTROL_M, mc->m);
 556         v = set_field(v, MCONTROL_H, mc->h);
 557         v = set_field(v, MCONTROL_S, mc->s);
 558         v = set_field(v, MCONTROL_U, mc->u);
 559         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 560         v = set_field(v, MCONTROL_STORE, mc->store);
 561         v = set_field(v, MCONTROL_LOAD, mc->load);
 562         return v;
 563       } else {
 564         return 0;
 565       }
 566       break;
 567     case CSR_TDATA2:
 568       if (state.tselect < state.num_triggers) {
 569         return state.tdata2[state.tselect];
 570       } else {
 571         return 0;
 572       }
 573       break;
 574     case CSR_TDATA3: return 0;
 575     case CSR_DCSR:
 576       {
 577         uint32_t v = 0;
 578         v = set_field(v, DCSR_XDEBUGVER, 1);
 579         v = set_field(v, DCSR_NDRESET, 0);
 580         v = set_field(v, DCSR_FULLRESET, 0);
 581         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 582         v = set_field(v, DCSR_STEP, state.dcsr.step);
 583         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 584         v = set_field(v, DCSR_STOPCYCLE, 0);
 585         v = set_field(v, DCSR_STOPTIME, 0);
 586         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 587         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 588         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 589         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 590         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 591         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 592         return v;
 593       }
 594     case CSR_DPC:
 595       return state.dpc;
 596     case CSR_DSCRATCH:
 597       return state.dscratch;
 598   }
 599   throw trap_illegal_instruction();
 600 }
 601
 602 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 603 {
 604   throw trap_illegal_instruction();
 605 }
 606
 607 insn_func_t processor_t::decode_insn(insn_t insn)
 608 {
 609   // look up opcode in hash table
 610   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 611   insn_desc_t desc = opcode_cache[idx];
 612
 613   if (unlikely(insn.bits() != desc.match)) {
 614     // fall back to linear search
 615     insn_desc_t* p = &instructions[0];
 616     while ((insn.bits() & p->mask) != p->match)
 617       p++;
 618     desc = *p;
 619
 620     if (p->mask != 0 && p > &instructions[0]) {
 621       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 622         // move to front of opcode list to reduce miss penalty
 623         while (--p >= &instructions[0])
 624           *(p+1) = *p;
 625         instructions[0] = desc;
 626       }
 627     }
 628
 629     opcode_cache[idx] = desc;
 630     opcode_cache[idx].match = insn.bits();
 631   }
 632
 633   return xlen == 64 ? desc.rv64 : desc.rv32;
 634 }
 635
 636 void processor_t::register_insn(insn_desc_t desc)
 637 {
 638   instructions.push_back(desc);
 639 }
 640
 641 void processor_t::build_opcode_map()
 642 {
 643   struct cmp {
 644     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 645       if (lhs.match == rhs.match)
 646         return lhs.mask > rhs.mask;
 647       return lhs.match > rhs.match;
 648     }
 649   };
 650   std::sort(instructions.begin(), instructions.end(), cmp());
 651
 652   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 653     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 654 }
 655
 656 void processor_t::register_extension(extension_t* x)
 657 {
 658   for (auto insn : x->get_instructions())
 659     register_insn(insn);
 660   build_opcode_map();
 661   for (auto disasm_insn : x->get_disasms())
 662     disassembler->add_insn(disasm_insn);
 663   if (ext != NULL)
 664     throw std::logic_error("only one extension may be registered");
 665   ext = x;
 666   x->set_processor(this);
 667 }
 668
 669 void processor_t::register_base_instructions()
 670 {
 671   #define DECLARE_INSN(name, match, mask) \
 672     insn_bits_t name##_match = (match), name##_mask = (mask);
 673   #include "encoding.h"
 674   #undef DECLARE_INSN
 675
 676   #define DEFINE_INSN(name) \
 677     REGISTER_INSN(this, name, name##_match, name##_mask)
 678   #include "insn_list.h"
 679   #undef DEFINE_INSN
 680
 681   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 682   build_opcode_map();
 683 }
 684
 685 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 686 {
 687   switch (addr)
 688   {
 689     case 0:
 690       if (len <= 4) {
 691         memset(bytes, 0, len);
 692         bytes[0] = get_field(state.mip, MIP_MSIP);
 693         return true;
 694       }
 695       break;
 696   }
 697
 698   return false;
 699 }
 700
 701 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 702 {
 703   switch (addr)
 704   {
 705     case 0:
 706       if (len <= 4) {
 707         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 708         return true;
 709       }
 710       break;
 711   }
 712
 713   return false;
 714 }
 715
 716 void processor_t::trigger_updated()
 717 {
 718   mmu->flush_tlb();
 719   mmu->check_triggers_fetch = false;
 720   mmu->check_triggers_load = false;
 721   mmu->check_triggers_store = false;
 722
 723   for (unsigned i = 0; i < state.num_triggers; i++) {
 724     if (state.mcontrol[i].execute) {
 725       mmu->check_triggers_fetch = true;
 726     }
 727     if (state.mcontrol[i].load) {
 728       mmu->check_triggers_load = true;
 729     }
 730     if (state.mcontrol[i].store) {
 731       mmu->check_triggers_store = true;
 732     }
 733   }
 734 }