riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   // advertise support for supervisor and user modes
 116   isa |= 1L << ('s' - 'a');
 117   isa |= 1L << ('u' - 'a');
 118
 119   max_isa = isa;
 120 }
 121
 122 void state_t::reset()
 123 {
 124   memset(this, 0, sizeof(*this));
 125   prv = PRV_M;
 126   pc = DEFAULT_RSTVEC;
 127   load_reservation = -1;
 128   tselect = 0;
 129   for (unsigned int i = 0; i < num_triggers; i++)
 130     mcontrol[i].type = 2;
 131 }
 132
 133 void processor_t::set_debug(bool value)
 134 {
 135   debug = value;
 136   if (ext)
 137     ext->set_debug(value);
 138 }
 139
 140 void processor_t::set_histogram(bool value)
 141 {
 142   histogram_enabled = value;
 143 #ifndef RISCV_ENABLE_HISTOGRAM
 144   if (value) {
 145     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 146     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 147   }
 148 #endif
 149 }
 150
 151 void processor_t::reset()
 152 {
 153   state.reset();
 154   state.dcsr.halt = halt_on_reset;
 155   halt_on_reset = false;
 156   set_csr(CSR_MSTATUS, state.mstatus);
 157
 158   if (ext)
 159     ext->reset(); // reset the extension
 160 }
 161
 162 // Count number of contiguous 0 bits starting from the LSB.
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt(reg_t pending_interrupts)
 173 {
 174   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 175   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 176   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 177
 178   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 179   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 180   if (enabled_interrupts == 0)
 181     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (state.dcsr.cause == 0 && enabled_interrupts)
 184     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 185 }
 186
 187 static int xlen_to_uxl(int xlen)
 188 {
 189   if (xlen == 32)
 190     return 1;
 191   if (xlen == 64)
 192     return 2;
 193   abort();
 194 }
 195
 196 reg_t processor_t::legalize_privilege(reg_t prv)
 197 {
 198   assert(prv <= PRV_M);
 199
 200   if (!supports_extension('U'))
 201     return PRV_M;
 202
 203   if (prv == PRV_H || !supports_extension('S'))
 204     return PRV_U;
 205
 206   return prv;
 207 }
 208
 209 void processor_t::set_privilege(reg_t prv)
 210 {
 211   mmu->flush_tlb();
 212   state.prv = legalize_privilege(prv);
 213 }
 214
 215 void processor_t::enter_debug_mode(uint8_t cause)
 216 {
 217   state.dcsr.cause = cause;
 218   state.dcsr.prv = state.prv;
 219   set_privilege(PRV_M);
 220   state.dpc = state.pc;
 221   state.pc = DEBUG_ROM_ENTRY;
 222 }
 223
 224 void processor_t::take_trap(trap_t& t, reg_t epc)
 225 {
 226   if (debug) {
 227     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 228             id, t.name(), epc);
 229     if (t.has_badaddr())
 230       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 231           t.get_badaddr());
 232   }
 233
 234   if (state.dcsr.cause) {
 235     if (t.cause() == CAUSE_BREAKPOINT) {
 236       state.pc = DEBUG_ROM_ENTRY;
 237     } else {
 238       state.pc = DEBUG_ROM_TVEC;
 239     }
 240     return;
 241   }
 242
 243   if (t.cause() == CAUSE_BREAKPOINT && (
 244               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 245               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 246               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 247     enter_debug_mode(DCSR_CAUSE_SWBP);
 248     return;
 249   }
 250
 251   // by default, trap to M-mode, unless delegated to S-mode
 252   reg_t bit = t.cause();
 253   reg_t deleg = state.medeleg;
 254   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 255   if (interrupt)
 256     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 257   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 258     // handle the trap in S-mode
 259     state.pc = state.stvec;
 260     state.scause = t.cause();
 261     state.sepc = epc;
 262     if (t.has_badaddr())
 263       state.sbadaddr = t.get_badaddr();
 264
 265     reg_t s = state.mstatus;
 266     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 267     s = set_field(s, MSTATUS_SPP, state.prv);
 268     s = set_field(s, MSTATUS_SIE, 0);
 269     set_csr(CSR_MSTATUS, s);
 270     set_privilege(PRV_S);
 271   } else {
 272     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 273     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 274     state.mepc = epc;
 275     state.mcause = t.cause();
 276     if (t.has_badaddr())
 277       state.mbadaddr = t.get_badaddr();
 278
 279     reg_t s = state.mstatus;
 280     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 281     s = set_field(s, MSTATUS_MPP, state.prv);
 282     s = set_field(s, MSTATUS_MIE, 0);
 283     set_csr(CSR_MSTATUS, s);
 284     set_privilege(PRV_M);
 285   }
 286
 287   yield_load_reservation();
 288 }
 289
 290 void processor_t::disasm(insn_t insn)
 291 {
 292   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 293   if (last_pc != state.pc || last_bits != bits) {
 294     if (executions != 1) {
 295       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 296     }
 297
 298     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 299             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 300     last_pc = state.pc;
 301     last_bits = bits;
 302     executions = 1;
 303   } else {
 304     executions++;
 305   }
 306 }
 307
 308 int processor_t::paddr_bits()
 309 {
 310   assert(xlen == max_xlen);
 311   return max_xlen == 64 ? 50 : 34;
 312 }
 313
 314 void processor_t::set_csr(int which, reg_t val)
 315 {
 316   val = zext_xlen(val);
 317   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 318   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 319   switch (which)
 320   {
 321     case CSR_FFLAGS:
 322       dirty_fp_state;
 323       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 324       break;
 325     case CSR_FRM:
 326       dirty_fp_state;
 327       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 328       break;
 329     case CSR_FCSR:
 330       dirty_fp_state;
 331       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 332       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 333       break;
 334     case CSR_MSTATUS: {
 335       if ((val ^ state.mstatus) &
 336           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 337         mmu->flush_tlb();
 338
 339       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 340                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 341                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 342                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 343                  (ext ? MSTATUS_XS : 0);
 344
 345       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 346       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 347       if (supports_extension('S'))
 348         mask |= MSTATUS_SPP;
 349
 350       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 351
 352       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 353       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 354       if (max_xlen == 32)
 355         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 356       else
 357         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 358
 359       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 360       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 361       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 362       // U-XLEN == S-XLEN == M-XLEN
 363       xlen = max_xlen;
 364       break;
 365     }
 366     case CSR_MIP: {
 367       reg_t mask = MIP_SSIP | MIP_STIP;
 368       state.mip = (state.mip & ~mask) | (val & mask);
 369       break;
 370     }
 371     case CSR_MIE:
 372       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 373       break;
 374     case CSR_MIDELEG:
 375       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 376       break;
 377     case CSR_MEDELEG: {
 378       reg_t mask =
 379         (1 << CAUSE_MISALIGNED_FETCH) |
 380         (1 << CAUSE_BREAKPOINT) |
 381         (1 << CAUSE_USER_ECALL) |
 382         (1 << CAUSE_FETCH_PAGE_FAULT) |
 383         (1 << CAUSE_LOAD_PAGE_FAULT) |
 384         (1 << CAUSE_STORE_PAGE_FAULT);
 385       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 386       break;
 387     }
 388     case CSR_MINSTRET:
 389     case CSR_MCYCLE:
 390       if (xlen == 32)
 391         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 392       else
 393         state.minstret = val;
 394       break;
 395     case CSR_MINSTRETH:
 396     case CSR_MCYCLEH:
 397       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 398       break;
 399     case CSR_SCOUNTEREN:
 400       state.scounteren = val;
 401       break;
 402     case CSR_MCOUNTEREN:
 403       state.mcounteren = val;
 404       break;
 405     case CSR_SSTATUS: {
 406       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 407                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 408       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 409     }
 410     case CSR_SIP: {
 411       reg_t mask = MIP_SSIP & state.mideleg;
 412       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 413     }
 414     case CSR_SIE:
 415       return set_csr(CSR_MIE,
 416                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 417     case CSR_SPTBR: {
 418       mmu->flush_tlb();
 419       if (max_xlen == 32)
 420         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 421       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 422                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 423                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 424         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 425       break;
 426     }
 427     case CSR_SEPC: state.sepc = val; break;
 428     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 429     case CSR_SSCRATCH: state.sscratch = val; break;
 430     case CSR_SCAUSE: state.scause = val; break;
 431     case CSR_SBADADDR: state.sbadaddr = val; break;
 432     case CSR_MEPC: state.mepc = val; break;
 433     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 434     case CSR_MSCRATCH: state.mscratch = val; break;
 435     case CSR_MCAUSE: state.mcause = val; break;
 436     case CSR_MBADADDR: state.mbadaddr = val; break;
 437     case CSR_MISA: {
 438       if (!(val & (1L << ('F' - 'A'))))
 439         val &= ~(1L << ('D' - 'A'));
 440
 441       // allow MAFDC bits in MISA to be modified
 442       reg_t mask = 0;
 443       mask |= 1L << ('M' - 'A');
 444       mask |= 1L << ('A' - 'A');
 445       mask |= 1L << ('F' - 'A');
 446       mask |= 1L << ('D' - 'A');
 447       mask |= 1L << ('C' - 'A');
 448       mask &= max_isa;
 449
 450       isa = (val & mask) | (isa & ~mask);
 451       break;
 452     }
 453     case CSR_TSELECT:
 454       if (val < state.num_triggers) {
 455         state.tselect = val;
 456       }
 457       break;
 458     case CSR_TDATA1:
 459       {
 460         mcontrol_t *mc = &state.mcontrol[state.tselect];
 461         if (mc->dmode && !state.dcsr.cause) {
 462           break;
 463         }
 464         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 465         mc->select = get_field(val, MCONTROL_SELECT);
 466         mc->timing = get_field(val, MCONTROL_TIMING);
 467         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 468         mc->chain = get_field(val, MCONTROL_CHAIN);
 469         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 470         mc->m = get_field(val, MCONTROL_M);
 471         mc->h = get_field(val, MCONTROL_H);
 472         mc->s = get_field(val, MCONTROL_S);
 473         mc->u = get_field(val, MCONTROL_U);
 474         mc->execute = get_field(val, MCONTROL_EXECUTE);
 475         mc->store = get_field(val, MCONTROL_STORE);
 476         mc->load = get_field(val, MCONTROL_LOAD);
 477         // Assume we're here because of csrw.
 478         if (mc->execute)
 479           mc->timing = 0;
 480         trigger_updated();
 481       }
 482       break;
 483     case CSR_TDATA2:
 484       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 485         break;
 486       }
 487       if (state.tselect < state.num_triggers) {
 488         state.tdata2[state.tselect] = val;
 489       }
 490       break;
 491     case CSR_DCSR:
 492       state.dcsr.prv = get_field(val, DCSR_PRV);
 493       state.dcsr.step = get_field(val, DCSR_STEP);
 494       // TODO: ndreset and fullreset
 495       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 496       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 497       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 498       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 499       state.dcsr.halt = get_field(val, DCSR_HALT);
 500       break;
 501     case CSR_DPC:
 502       state.dpc = val;
 503       break;
 504     case CSR_DSCRATCH:
 505       state.dscratch = val;
 506       break;
 507   }
 508 }
 509
 510 reg_t processor_t::get_csr(int which)
 511 {
 512   uint32_t ctr_en = -1;
 513   if (state.prv < PRV_M)
 514     ctr_en &= state.mcounteren;
 515   if (state.prv < PRV_S)
 516     ctr_en &= state.scounteren;
 517   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 518
 519   if (ctr_ok) {
 520     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 521       return 0;
 522     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 523       return 0;
 524   }
 525   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 526     return 0;
 527   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 528     return 0;
 529   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 530     return 0;
 531
 532   switch (which)
 533   {
 534     case CSR_FFLAGS:
 535       require_fp;
 536       if (!supports_extension('F'))
 537         break;
 538       return state.fflags;
 539     case CSR_FRM:
 540       require_fp;
 541       if (!supports_extension('F'))
 542         break;
 543       return state.frm;
 544     case CSR_FCSR:
 545       require_fp;
 546       if (!supports_extension('F'))
 547         break;
 548       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 549     case CSR_INSTRET:
 550     case CSR_CYCLE:
 551       if (ctr_ok)
 552         return state.minstret;
 553       break;
 554     case CSR_MINSTRET:
 555     case CSR_MCYCLE:
 556       return state.minstret;
 557     case CSR_MINSTRETH:
 558     case CSR_MCYCLEH:
 559       if (xlen == 32)
 560         return state.minstret >> 32;
 561       break;
 562     case CSR_SCOUNTEREN: return state.scounteren;
 563     case CSR_MCOUNTEREN: return state.mcounteren;
 564     case CSR_SSTATUS: {
 565       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 566                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 567       reg_t sstatus = state.mstatus & mask;
 568       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 569           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 570         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 571       return sstatus;
 572     }
 573     case CSR_SIP: return state.mip & state.mideleg;
 574     case CSR_SIE: return state.mie & state.mideleg;
 575     case CSR_SEPC: return state.sepc;
 576     case CSR_SBADADDR: return state.sbadaddr;
 577     case CSR_STVEC: return state.stvec;
 578     case CSR_SCAUSE:
 579       if (max_xlen > xlen)
 580         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 581       return state.scause;
 582     case CSR_SPTBR:
 583       if (get_field(state.mstatus, MSTATUS_TVM))
 584         require_privilege(PRV_M);
 585       return state.sptbr;
 586     case CSR_SSCRATCH: return state.sscratch;
 587     case CSR_MSTATUS: return state.mstatus;
 588     case CSR_MIP: return state.mip;
 589     case CSR_MIE: return state.mie;
 590     case CSR_MEPC: return state.mepc;
 591     case CSR_MSCRATCH: return state.mscratch;
 592     case CSR_MCAUSE: return state.mcause;
 593     case CSR_MBADADDR: return state.mbadaddr;
 594     case CSR_MISA: return isa;
 595     case CSR_MARCHID: return 0;
 596     case CSR_MIMPID: return 0;
 597     case CSR_MVENDORID: return 0;
 598     case CSR_MHARTID: return id;
 599     case CSR_MTVEC: return state.mtvec;
 600     case CSR_MEDELEG: return state.medeleg;
 601     case CSR_MIDELEG: return state.mideleg;
 602     case CSR_TSELECT: return state.tselect;
 603     case CSR_TDATA1:
 604       if (state.tselect < state.num_triggers) {
 605         reg_t v = 0;
 606         mcontrol_t *mc = &state.mcontrol[state.tselect];
 607         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 608         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 609         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 610         v = set_field(v, MCONTROL_SELECT, mc->select);
 611         v = set_field(v, MCONTROL_TIMING, mc->timing);
 612         v = set_field(v, MCONTROL_ACTION, mc->action);
 613         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 614         v = set_field(v, MCONTROL_MATCH, mc->match);
 615         v = set_field(v, MCONTROL_M, mc->m);
 616         v = set_field(v, MCONTROL_H, mc->h);
 617         v = set_field(v, MCONTROL_S, mc->s);
 618         v = set_field(v, MCONTROL_U, mc->u);
 619         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 620         v = set_field(v, MCONTROL_STORE, mc->store);
 621         v = set_field(v, MCONTROL_LOAD, mc->load);
 622         return v;
 623       } else {
 624         return 0;
 625       }
 626       break;
 627     case CSR_TDATA2:
 628       if (state.tselect < state.num_triggers) {
 629         return state.tdata2[state.tselect];
 630       } else {
 631         return 0;
 632       }
 633       break;
 634     case CSR_TDATA3: return 0;
 635     case CSR_DCSR:
 636       {
 637         uint32_t v = 0;
 638         v = set_field(v, DCSR_XDEBUGVER, 1);
 639         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 640         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 641         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 642         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 643         v = set_field(v, DCSR_STOPCYCLE, 0);
 644         v = set_field(v, DCSR_STOPTIME, 0);
 645         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 646         v = set_field(v, DCSR_STEP, state.dcsr.step);
 647         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 648         return v;
 649       }
 650     case CSR_DPC:
 651       return state.dpc;
 652     case CSR_DSCRATCH:
 653       return state.dscratch;
 654   }
 655   throw trap_illegal_instruction(0);
 656 }
 657
 658 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 659 {
 660   throw trap_illegal_instruction(0);
 661 }
 662
 663 insn_func_t processor_t::decode_insn(insn_t insn)
 664 {
 665   // look up opcode in hash table
 666   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 667   insn_desc_t desc = opcode_cache[idx];
 668
 669   if (unlikely(insn.bits() != desc.match)) {
 670     // fall back to linear search
 671     insn_desc_t* p = &instructions[0];
 672     while ((insn.bits() & p->mask) != p->match)
 673       p++;
 674     desc = *p;
 675
 676     if (p->mask != 0 && p > &instructions[0]) {
 677       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 678         // move to front of opcode list to reduce miss penalty
 679         while (--p >= &instructions[0])
 680           *(p+1) = *p;
 681         instructions[0] = desc;
 682       }
 683     }
 684
 685     opcode_cache[idx] = desc;
 686     opcode_cache[idx].match = insn.bits();
 687   }
 688
 689   return xlen == 64 ? desc.rv64 : desc.rv32;
 690 }
 691
 692 void processor_t::register_insn(insn_desc_t desc)
 693 {
 694   instructions.push_back(desc);
 695 }
 696
 697 void processor_t::build_opcode_map()
 698 {
 699   struct cmp {
 700     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 701       if (lhs.match == rhs.match)
 702         return lhs.mask > rhs.mask;
 703       return lhs.match > rhs.match;
 704     }
 705   };
 706   std::sort(instructions.begin(), instructions.end(), cmp());
 707
 708   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 709     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 710 }
 711
 712 void processor_t::register_extension(extension_t* x)
 713 {
 714   for (auto insn : x->get_instructions())
 715     register_insn(insn);
 716   build_opcode_map();
 717   for (auto disasm_insn : x->get_disasms())
 718     disassembler->add_insn(disasm_insn);
 719   if (ext != NULL)
 720     throw std::logic_error("only one extension may be registered");
 721   ext = x;
 722   x->set_processor(this);
 723 }
 724
 725 void processor_t::register_base_instructions()
 726 {
 727   #define DECLARE_INSN(name, match, mask) \
 728     insn_bits_t name##_match = (match), name##_mask = (mask);
 729   #include "encoding.h"
 730   #undef DECLARE_INSN
 731
 732   #define DEFINE_INSN(name) \
 733     REGISTER_INSN(this, name, name##_match, name##_mask)
 734   #include "insn_list.h"
 735   #undef DEFINE_INSN
 736
 737   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 738   build_opcode_map();
 739 }
 740
 741 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 742 {
 743   switch (addr)
 744   {
 745     case 0:
 746       if (len <= 4) {
 747         memset(bytes, 0, len);
 748         bytes[0] = get_field(state.mip, MIP_MSIP);
 749         return true;
 750       }
 751       break;
 752   }
 753
 754   return false;
 755 }
 756
 757 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 758 {
 759   switch (addr)
 760   {
 761     case 0:
 762       if (len <= 4) {
 763         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 764         return true;
 765       }
 766       break;
 767   }
 768
 769   return false;
 770 }
 771
 772 void processor_t::trigger_updated()
 773 {
 774   mmu->flush_tlb();
 775   mmu->check_triggers_fetch = false;
 776   mmu->check_triggers_load = false;
 777   mmu->check_triggers_store = false;
 778
 779   for (unsigned i = 0; i < state.num_triggers; i++) {
 780     if (state.mcontrol[i].execute) {
 781       mmu->check_triggers_fetch = true;
 782     }
 783     if (state.mcontrol[i].load) {
 784       mmu->check_triggers_load = true;
 785     }
 786     if (state.mcontrol[i].store) {
 787       mmu->check_triggers_store = true;
 788     }
 789   }
 790 }