riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include "gdbserver.h"
   7 #include <map>
   8 #include <iostream>
   9 #include <sstream>
  10 #include <climits>
  11 #include <cstdlib>
  12 #include <cassert>
  13 #include <signal.h>
  14
  15 volatile bool ctrlc_pressed = false;
  16 static void handle_signal(int sig)
  17 {
  18   if (ctrlc_pressed)
  19     exit(-1);
  20   ctrlc_pressed = true;
  21   signal(sig, &handle_signal);
  22 }
  23
  24 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  25              const std::vector<std::string>& args)
  26   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  27     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  28 {
  29   signal(SIGINT, &handle_signal);
  30   // allocate target machine's memory, shrinking it as necessary
  31   // until the allocation succeeds
  32   size_t memsz0 = (size_t)mem_mb << 20;
  33   size_t quantum = 1L << 20;
  34   if (memsz0 == 0)
  35     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  36
  37   memsz = memsz0;
  38   while ((mem = (char*)calloc(1, memsz)) == NULL)
  39     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  40
  41   if (memsz != memsz0)
  42     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  43             (unsigned long)memsz, (unsigned long)memsz0);
  44
  45   bus.add_device(DEBUG_START, &debug_module);
  46
  47   debug_mmu = new mmu_t(this, NULL);
  48
  49   for (size_t i = 0; i < procs.size(); i++) {
  50     procs[i] = new processor_t(isa, this, i);
  51     if (halted)
  52       procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
  53   }
  54
  55   rtc.reset(new rtc_t(procs));
  56   make_config_string();
  57 }
  58
  59 sim_t::~sim_t()
  60 {
  61   for (size_t i = 0; i < procs.size(); i++)
  62     delete procs[i];
  63   delete debug_mmu;
  64   free(mem);
  65 }
  66
  67 int sim_t::run()
  68 {
  69   if (!debug && log)
  70     set_procs_debug(true);
  71   while (htif->tick())
  72   {
  73     if (debug || ctrlc_pressed)
  74       interactive();
  75     else
  76       step(INTERLEAVE);
  77     if (gdbserver) {
  78         gdbserver->handle();
  79     }
  80   }
  81   return htif->exit_code();
  82 }
  83
  84 void sim_t::step(size_t n)
  85 {
  86   for (size_t i = 0, steps = 0; i < n; i += steps)
  87   {
  88     steps = std::min(n - i, INTERLEAVE - current_step);
  89     procs[current_proc]->step(steps);
  90
  91     current_step += steps;
  92     if (current_step == INTERLEAVE)
  93     {
  94       current_step = 0;
  95       procs[current_proc]->yield_load_reservation();
  96       if (++current_proc == procs.size()) {
  97         current_proc = 0;
  98         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
  99       }
 100
 101       htif->tick();
 102     }
 103   }
 104 }
 105
 106 bool sim_t::running()
 107 {
 108   for (size_t i = 0; i < procs.size(); i++)
 109     if (procs[i]->running())
 110       return true;
 111   return false;
 112 }
 113
 114 void sim_t::set_debug(bool value)
 115 {
 116   debug = value;
 117 }
 118
 119 void sim_t::set_log(bool value)
 120 {
 121   log = value;
 122 }
 123
 124 void sim_t::set_histogram(bool value)
 125 {
 126   histogram_enabled = value;
 127   for (size_t i = 0; i < procs.size(); i++) {
 128     procs[i]->set_histogram(histogram_enabled);
 129   }
 130 }
 131
 132 void sim_t::set_procs_debug(bool value)
 133 {
 134   for (size_t i=0; i< procs.size(); i++)
 135     procs[i]->set_debug(value);
 136 }
 137
 138 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 139 {
 140   if (addr + len < addr)
 141     return false;
 142   return bus.load(addr, len, bytes);
 143 }
 144
 145 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 146 {
 147   if (addr + len < addr)
 148     return false;
 149   return bus.store(addr, len, bytes);
 150 }
 151
 152 void sim_t::make_config_string()
 153 {
 154   reg_t rtc_addr = EXT_IO_BASE;
 155   bus.add_device(rtc_addr, rtc.get());
 156
 157   const int align = 0x1000;
 158   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 159   reg_t cpu_size = align;
 160
 161   uint32_t reset_vec[8] = {
 162     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 163     0x00028067,                         //   jump straight to DRAM_BASE
 164     0x00000000,                         // reserved
 165     0,                                  // config string pointer
 166     0, 0, 0, 0                          // trap vector
 167   };
 168   reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 169
 170   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 171
 172   std::stringstream s;
 173   s << std::hex <<
 174         "platform {\n"
 175         "  vendor ucb;\n"
 176         "  arch spike;\n"
 177         "};\n"
 178         "rtc {\n"
 179         "  addr 0x" << rtc_addr << ";\n"
 180         "};\n"
 181         "ram {\n"
 182         "  0 {\n"
 183         "    addr 0x" << DRAM_BASE << ";\n"
 184         "    size 0x" << memsz << ";\n"
 185         "  };\n"
 186         "};\n"
 187         "core {\n";
 188   for (size_t i = 0; i < procs.size(); i++) {
 189     s <<
 190         "  " << i << " {\n"
 191         "    " << "0 {\n" << // hart 0 on core i
 192         "      isa " << procs[i]->isa_string << ";\n"
 193         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 194         "      ipi 0x" << cpu_addr << ";\n"
 195         "    };\n"
 196         "  };\n";
 197     bus.add_device(cpu_addr, procs[i]);
 198     cpu_addr += cpu_size;
 199   }
 200   s <<  "};\n";
 201
 202   config_string = s.str();
 203   rom.insert(rom.end(), config_string.begin(), config_string.end());
 204   rom.resize((rom.size() / align + 1) * align);
 205
 206   boot_rom.reset(new rom_device_t(rom));
 207   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 208 }