Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fcvt_d_s.h

diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index ec778cc92f475446212fca675014dff066076b26..5f805b061472c89dabdb25af51fb69a3fe1eefa1 100644 (file)
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)).v);
+WRITE_FRD(f32_to_f64(f32(FRS1)));
 set_fp_exceptions;