Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmax_s.h

diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index bf90356b6748c68b22dfb1f5eb4f2b2e3a64f464..2f570ead5432c040bb29459c8f84efbd4ea00e60 100644 (file)
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,6 +1,6 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF32UI);
+WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;