Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmin_d.h

diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 2a1755e30eb6db78cc1a43cb91e3796344545a82..cd40e159984ab7c7953bf82aeaf213bad47b06bf 100644 (file)
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,6 +1,6 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(FRS2) ? FRS1 : FRS2);
-if ((isNaNF64UI(FRS1) && isNaNF64UI(FRS2)) || softfloat_exceptionFlags)
-  WRITE_FRD(defaultNaNF64UI);
+WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+  WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;