Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmsub_d.h

diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index afcea88e693d77b3c90d6a7351304d29bff8e43a..5b5bc0f75e4c9c26a42b35409df98d6de063c9c3 100644 (file)
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
+WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
 set_fp_exceptions;