Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fmul_s.h

diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index 9ae7b3c64edbbd65c971055607937b54c0e96a9a..145d5ce4d96fcc4e9d387f9817359ea1baa6f6f9 100644 (file)
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;