Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fnmsub_s.h

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 3e0b8ea7ce37c85e1c6220fdefcc717e0a9cd9ba..4c61fc7c81170175929bd556095ed97481e9c135 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v);
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
 set_fp_exceptions;