Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fsqrt_d.h

diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 45f37ce00ae010d2e3b7733e7334084d0d7e9b16..da138ba1937f53070d05f81beb096a765580c457 100644 (file)
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sqrt(f64(FRS1)).v);
+WRITE_FRD(f64_sqrt(f64(FRS1)));
 set_fp_exceptions;