Implement new FP encoding

[riscv-isa-sim.git] / riscv / insns / fsub_s.h

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index e7a7cf1824ccb7e5d57575e621c39514e98e6c00..f6183ea000965c87f50db9491a9242a5139cef53 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)).v);
+WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;