| 2011-06-11 |
Andrew Waterman | [xcc] cleaned up mmu code |
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| 2011-06-06 |
Andrew Waterman | [sim] fix writeback after ipi clearing |
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| 2011-06-05 |
Andrew Waterman | [sim] add ability to clear IPIs |
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| 2011-05-29 |
Andrew Waterman | [fesvr,xcc,sim] fixed multicore sim for akaros |
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| 2011-05-18 |
Yunsup Lee | [opcodes,pk,sim] add more vector traps (for #banks... |
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| 2011-05-16 |
Andrew Waterman | [sim,pk] cleanups & initial virtual memory support |
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| 2011-01-19 |
Andrew Waterman | [opcodes, sim, xcc] made *w insns illegal in RV32 |
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| 2010-11-22 |
Andrew Waterman | [xcc, sim, pk, opcodes] new instruction encoding! |
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| 2010-10-05 |
Andrew Waterman | [xcc,sim] eliminated vectored traps |
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| 2010-09-21 |
Andrew Waterman | [xcc, sim] changed instruction format so imm12 subs... |
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| 2010-09-09 |
Andrew Waterman | Merge branch 'master' of /project/eecs/parlab/git/proje... |
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| 2010-09-09 |
Andrew Waterman | [pk, sim] added interrupt support to sim; added timer... |
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| 2010-09-08 |
Yunsup Lee | [sim] add while to interactive_until |
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| 2010-09-07 |
Andrew Waterman | [sim, xcc] added PCRs to replace k0 and k1 |
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| 2010-09-07 |
Andrew Waterman | [sim, xcc] bthread threading model exposed; insn encodi... |
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| 2010-08-24 |
Andrew Waterman | [sim] privileged mode support for 32-bit operation |
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| 2010-08-04 |
Andrew Waterman | [pk,sim,xcc] Renamed instructions to RISC-V spec |
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projects / riscv-isa-sim.git / history