[xcc] minor performance tweaks
[riscv-isa-sim.git] / riscv / sim.cc
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2010-12-27 Andrew Waterman[sim] fixed some compiler warnings
2010-11-22 Andrew Waterman[xcc, sim, pk] link register is now x1
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-08 Yunsup Lee[sim] change applink for tohost/fromhost
2010-09-07 Andrew Waterman[sim] fixed bug in msub.d; added ability to print FPRs...
2010-08-10 Andrew Waterman[sim] removed unused elf loader
2010-07-23 Yunsup Lee[sim] various fixes to get the sim work with the fesvr
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure