git.libre-soc.org Git - riscv-isa-sim.git/search

2017-03-22	Wesley W. Terpstra	sim: declare cores as interrupt-controllers for clint	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	bootrom: set a0 to hartid and a1 to dtb before boot	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	configstring: rename variables to dts	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	riscv: remove dependency on num_cores	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	bootrom: include compiled dtb	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	sim: create DTS instead of config string	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	sim: define emulated CPU clock rate to be 1GHz	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	autoconf: put location of 'dtc' into config.h	commit \| commitdiff \| tree

Simple-V augmented version of spike