sim: declare cores as interrupt-controllers for clint
authorWesley W. Terpstra <wesley@sifive.com>
Wed, 22 Mar 2017 03:53:09 +0000 (20:53 -0700)
committerWesley W. Terpstra <wesley@sifive.com>
Wed, 22 Mar 2017 03:53:09 +0000 (20:53 -0700)
riscv/sim.cc

index a2b5cd1c359b7821f11fa3de070ea9ff834d4fba..bdf55e275bfec0e937c9804fe49e92610b982cc8 100644 (file)
@@ -276,6 +276,8 @@ void sim_t::make_dtb()
          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
          "      clock-frequency = <" << CPU_HZ << ">;\n"
+         "      interrupt-controller;\n"
+         "      #interrupt-cells = <1>;\n"
          "    };\n";
   }
   reg_t membs = DRAM_BASE;