cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156
 157 class Misa:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class Fetch:
 172     def __init__(self, comb, sync):
 173         self.comb = comb
 174         self.sync = sync
 175         self.action = Signal(fetch_action, name="fetch_action")
 176         self.target_pc = Signal(32, name="fetch_target_pc")
 177         self.output_pc = Signal(32, name="fetch_output_pc")
 178         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 179         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 180
 181     def get_fetch_action(self, dc, load_store_misaligned, mi,
 182                          branch_taken, misaligned_jump_target,
 183                          csr_op_is_valid):
 184         c = {}
 185         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 186         c[FOS.empty] = self.action.eq(FA.default)
 187         c[FOS.trap] = self.action.eq(FA.ack_trap)
 188
 189         # illegal instruction -> error trap
 190         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 191                  self.action.eq(FA.error_trap)
 192               )
 193
 194         # ecall / ebreak -> noerror trap
 195         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 196                  self.action.eq(FA.noerror_trap))
 197
 198         # load/store: check alignment, check wait
 199         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 200                 If((load_store_misaligned | ~mi.rw_address_valid),
 201                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 202                 ).Elif(mi.rw_wait,
 203                     self.action.eq(FA.wait) # wait
 204                 ).Else(
 205                     self.action.eq(FA.default) # ok
 206                 )
 207               )
 208
 209         # fence
 210         i = i.Elif((dc.act & DA.fence) != 0,
 211                  self.action.eq(FA.fence))
 212
 213         # branch -> misaligned=error, otherwise jump
 214         i = i.Elif((dc.act & DA.branch) != 0,
 215                 If(misaligned_jump_target,
 216                     self.action.eq(FA.error_trap)
 217                 ).Else(
 218                     self.action.eq(FA.jump)
 219                 )
 220               )
 221
 222         # jal/jalr -> misaligned=error, otherwise jump
 223         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 224                 If(misaligned_jump_target,
 225                     self.action.eq(FA.error_trap)
 226                 ).Else(
 227                     self.action.eq(FA.jump)
 228                 )
 229               )
 230
 231         # csr -> opvalid=ok, else error trap
 232         i = i.Elif((dc.act & DA.csr) != 0,
 233                 If(csr_op_is_valid,
 234                     self.action.eq(FA.default)
 235                 ).Else(
 236                     self.action.eq(FA.error_trap)
 237                 )
 238               )
 239
 240         c[FOS.valid] = i
 241
 242         return Case(self.output_state, c)
 243
 244 class CSR:
 245     def __init__(self, comb, sync, dc, register_rs1):
 246         self.comb = comb
 247         self.sync = sync
 248         self.number = Signal(12, name="csr_number")
 249         self.input_value = Signal(32, name="csr_input_value")
 250         self.reads = Signal(name="csr_reads")
 251         self.writes = Signal(name="csr_writes")
 252         self.op_is_valid = Signal(name="csr_op_is_valid")
 253
 254         self.comb += self.number.eq(dc.immediate)
 255         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 256                                             dc.rs1,
 257                                             register_rs1))
 258         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 259         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 260
 261         self.comb += self.get_csr_op_is_valid()
 262
 263     def get_csr_op_is_valid(self):
 264         """ determines if a CSR is valid
 265         """
 266         c = {}
 267         # invalid csrs
 268         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 269                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 270                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 271                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 272                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 273                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 274                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 275             c[f] = self.op_is_valid.eq(0)
 276
 277         # not-writeable -> ok
 278         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 279                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 280                   csr_mimpid, csr_mhartid]:
 281             c[f] = self.op_is_valid.eq(~self.writes)
 282
 283         # valid csrs
 284         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 285                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 286             c[f] = self.op_is_valid.eq(1)
 287
 288         # not implemented / default
 289         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 290                   csr_mcycleh, csr_minstreth, "default"]:
 291             c[f] = self.op_is_valid.eq(0)
 292
 293         return Case(self.number, c)
 294
 295     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 296         c = { "default": Constant(0, 32)}
 297         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 298         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 299         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 300         return Case(funct3, c)
 301
 302
 303 class MInfo:
 304     def __init__(self, comb):
 305         self.comb = comb
 306         # TODO
 307         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 308         self.time_counter    = Signal(64); # TODO: implement time_counter
 309         self.instret_counter = Signal(64); # TODO: implement instret_counter
 310
 311         self.mvendorid = Signal(32)
 312         self.marchid = Signal(32)
 313         self.mimpid = Signal(32)
 314         self.mhartid = Signal(32)
 315         self.comb += self.mvendorid.eq(Constant(0, 32))
 316         self.comb += self.marchid.eq(Constant(0, 32))
 317         self.comb += self.mimpid.eq(Constant(0, 32))
 318         self.comb += self.mhartid.eq(Constant(0, 32))
 319
 320
 321 class CPU(Module):
 322     """
 323     """
 324
 325     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 326         """ returns whether a load/store is misaligned
 327         """
 328         return Case(funct3[:2],
 329                 { F3.sb: ls.eq(Constant(0)),
 330                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 331                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 332                   "default": ls.eq(Constant(1))
 333                 })
 334
 335     def get_lsbm(self, dc):
 336         return Cat(Constant(1),
 337                    Mux((dc.funct3[1] | dc.funct3[0]),
 338                        Constant(1), Constant(0)),
 339                    Mux((dc.funct3[1]),
 340                        Constant(0b11, 2), Constant(0, 2)))
 341
 342     # XXX this happens to get done by various self.sync actions
 343     #def reset_to_initial(self, m, mstatus, mie, registers):
 344     #    return [m.mcause.eq(0),
 345     #            ]
 346
 347     def write_register(self, register_number, value):
 348         return If(register_number != 0,
 349                   self.registers[register_number].eq(value)
 350                )
 351
 352     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 353         s = [ms.mpie.eq(ms.mie),
 354              ms.mie.eq(0),
 355              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 356                            ft.output_pc + 4,
 357                            ft.output_pc))]
 358
 359         # fetch action ack trap
 360         i = If(ft.action == FA.ack_trap,
 361                 m.mcause.eq(cause_instruction_access_fault)
 362               )
 363
 364         # ecall/ebreak
 365         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 366                 m.mcause.eq(Mux(dc.immediate[0],
 367                                 cause_machine_environment_call,
 368                                 cause_breakpoint))
 369               )
 370
 371         # load
 372         i = i.Elif((dc.act & DA.load) != 0,
 373                 If(load_store_misaligned,
 374                     m.mcause.eq(cause_load_address_misaligned)
 375                 ).Else(
 376                     m.mcause.eq(cause_load_access_fault)
 377                 )
 378               )
 379
 380         # store
 381         i = i.Elif((dc.act & DA.store) != 0,
 382                 If(load_store_misaligned,
 383                     m.mcause.eq(cause_store_amo_address_misaligned)
 384                 ).Else(
 385                     m.mcause.eq(cause_store_amo_access_fault)
 386                 )
 387               )
 388
 389         # jal/jalr -> misaligned=error, otherwise jump
 390         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 391                 m.mcause.eq(cause_instruction_address_misaligned)
 392               )
 393
 394         # defaults to illegal instruction
 395         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 396
 397         s.append(i)
 398         return s
 399
 400     def main_block(self, minfo, csr, mi, m, mstatus, ft, dc,
 401                          load_store_misaligned,
 402                          loaded_value, alu_result,
 403                          lui_auipc_result):
 404         c = {}
 405         c[FOS.empty] = []
 406         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 407                                        load_store_misaligned)
 408         c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc,
 409                                        load_store_misaligned,
 410                                        loaded_value,
 411                                        alu_result,
 412                                        lui_auipc_result)
 413         return Case(ft.output_state, c)
 414
 415     def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc,
 416                            load_store_misaligned,
 417                            loaded_value, alu_result,
 418                            lui_auipc_result):
 419         # fetch action ack trap
 420         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 421                 self.handle_trap(m, mstatus, ft, dc,
 422                                        load_store_misaligned)
 423               )
 424
 425         # load
 426         i = i.Elif((dc.act & DA.load) != 0,
 427                 If(~mi.rw_wait,
 428                     self.write_register(dc.rd, loaded_value)
 429                 )
 430               )
 431
 432         # op or op_immediate
 433         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 434                 self.write_register(dc.rd, alu_result)
 435               )
 436
 437         # lui or auipc
 438         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 439                 self.write_register(dc.rd, lui_auipc_result)
 440               )
 441
 442         # jal/jalr
 443         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 444                 self.write_register(dc.rd, ft.output_pc + 4)
 445               )
 446
 447         i = i.Elif((dc.act & DA.csr) != 0,
 448                 self.handle_csr(minfo, mstatus, dc, csr)
 449               )
 450
 451         # fence, store, branch
 452         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 453                               DA.store | DA.branch)) != 0,
 454                 # do nothing
 455               )
 456
 457         return i
 458
 459     def handle_csr(self, minfo, mstatus, dc, csr):
 460         csr_output_value = Signal()
 461         csr_written_value = Signal()
 462         c = {}
 463
 464         # cycle
 465         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 466         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 467         # time
 468         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 469         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 470         # instret
 471         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 472         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 473         # mvendorid/march/mimpl/mhart
 474         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 475         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 476         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 477         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 478
 479         return Case(csr.number, c)
 480
 481         """
 482                 `csr_misa: begin
 483                     csr_output_value = misa;
 484                 end
 485                 `csr_mstatus: begin
 486                     csr_output_value = make_mstatus(mstatus_tsr,
 487                                                     mstatus_tw,
 488                                                     mstatus_tvm,
 489                                                     mstatus_mxr,
 490                                                     mstatus_sum,
 491                                                     mstatus_mprv,
 492                                                     mstatus_xs,
 493                                                     mstatus_fs,
 494                                                     mstatus_mpp,
 495                                                     mstatus_spp,
 496                                                     mstatus_mpie,
 497                                                     mstatus_spie,
 498                                                     mstatus_upie,
 499                                                     mstatus_mie,
 500                                                     mstatus_sie,
 501                                                     mstatus_uie);
 502                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 503                     if(csr_writes) begin
 504                         mstatus_mpie = csr_written_value[7];
 505                         mstatus_mie = csr_written_value[3];
 506                     end
 507                 end
 508                 `csr_mie: begin
 509                     csr_output_value = 0;
 510                     csr_output_value[11] = mie_meie;
 511                     csr_output_value[9] = mie_seie;
 512                     csr_output_value[8] = mie_ueie;
 513                     csr_output_value[7] = mie_mtie;
 514                     csr_output_value[5] = mie_stie;
 515                     csr_output_value[4] = mie_utie;
 516                     csr_output_value[3] = mie_msie;
 517                     csr_output_value[1] = mie_ssie;
 518                     csr_output_value[0] = mie_usie;
 519                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 520                     if(csr_writes) begin
 521                         mie_meie = csr_written_value[11];
 522                         mie_mtie = csr_written_value[7];
 523                         mie_msie = csr_written_value[3];
 524                     end
 525                 end
 526                 `csr_mtvec: begin
 527                     csr_output_value = mtvec;
 528                 end
 529                 `csr_mscratch: begin
 530                     csr_output_value = mscratch;
 531                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 532                     if(csr_writes)
 533                         mscratch = csr_written_value;
 534                 end
 535                 `csr_mepc: begin
 536                     csr_output_value = mepc;
 537                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 538                     if(csr_writes)
 539                         mepc = csr_written_value;
 540                 end
 541                 `csr_mcause: begin
 542                     csr_output_value = mcause;
 543                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 544                     if(csr_writes)
 545                         mcause = csr_written_value;
 546                 end
 547                 `csr_mip: begin
 548                     csr_output_value = 0;
 549                     csr_output_value[11] = mip_meip;
 550                     csr_output_value[9] = mip_seip;
 551                     csr_output_value[8] = mip_ueip;
 552                     csr_output_value[7] = mip_mtip;
 553                     csr_output_value[5] = mip_stip;
 554                     csr_output_value[4] = mip_utip;
 555                     csr_output_value[3] = mip_msip;
 556                     csr_output_value[1] = mip_ssip;
 557                     csr_output_value[0] = mip_usip;
 558                 end
 559                 endcase
 560                 if(csr_reads)
 561                     write_register(decoder_rd, csr_output_value);
 562             end
 563         end
 564         endcase
 565     end
 566         """
 567     def __init__(self):
 568         self.clk = ClockSignal()
 569         self.reset = ResetSignal()
 570         self.tty_write = Signal()
 571         self.tty_write_data = Signal(8)
 572         self.tty_write_busy = Signal()
 573         self.switch_2 = Signal()
 574         self.switch_3 = Signal()
 575         self.led_1 = Signal()
 576         self.led_3 = Signal()
 577
 578         ram_size = Constant(0x8000)
 579         ram_start = Constant(0x10000, 32)
 580         reset_vector = Signal(32)
 581         mtvec = Signal(32)
 582
 583         reset_vector.eq(ram_start)
 584         mtvec.eq(ram_start + 0x40)
 585
 586         l = []
 587         for i in range(31):
 588             r = Signal(32, name="register%d" % i)
 589             l.append(r)
 590             self.sync += r.eq(Constant(0, 32))
 591         self.registers = Array(l)
 592
 593         mi = MemoryInterface()
 594
 595         mii = Instance("cpu_memory_interface", name="memory_instance",
 596                     p_ram_size = ram_size,
 597                     p_ram_start = ram_start,
 598                     i_clk=ClockSignal(),
 599                     i_rst=ResetSignal(),
 600                     i_fetch_address = mi.fetch_address,
 601                     o_fetch_data = mi.fetch_data,
 602                     o_fetch_valid = mi.fetch_valid,
 603                     i_rw_address = mi.rw_address,
 604                     i_rw_byte_mask = mi.rw_byte_mask,
 605                     i_rw_read_not_write = mi.rw_read_not_write,
 606                     i_rw_active = mi.rw_active,
 607                     i_rw_data_in = mi.rw_data_in,
 608                     o_rw_data_out = mi.rw_data_out,
 609                     o_rw_address_valid = mi.rw_address_valid,
 610                     o_rw_wait = mi.rw_wait,
 611                     o_tty_write = self.tty_write,
 612                     o_tty_write_data = self.tty_write_data,
 613                     i_tty_write_busy = self.tty_write_busy,
 614                     i_switch_2 = self.switch_2,
 615                     i_switch_3 = self.switch_3,
 616                     o_led_1 = self.led_1,
 617                     o_led_3 = self.led_3
 618                   )
 619         self.specials += mii
 620
 621         ft = Fetch(self.comb, self.sync)
 622
 623         fs = Instance("CPUFetchStage", name="fetch_stage",
 624             i_clk=ClockSignal(),
 625             i_rst=ResetSignal(),
 626             o_memory_interface_fetch_address = mi.fetch_address,
 627             i_memory_interface_fetch_data = mi.fetch_data,
 628             i_memory_interface_fetch_valid = mi.fetch_valid,
 629             i_fetch_action = ft.action,
 630             i_target_pc = ft.target_pc,
 631             o_output_pc = ft.output_pc,
 632             o_output_instruction = ft.output_instruction,
 633             o_output_state = ft.output_state,
 634             i_reset_vector = reset_vector,
 635             i_mtvec = mtvec,
 636         )
 637         self.specials += fs
 638
 639         dc = Decoder()
 640
 641         cd = Instance("CPUDecoder", name="decoder",
 642             i_instruction = ft.output_instruction,
 643             o_funct7 = dc.funct7,
 644             o_funct3 = dc.funct3,
 645             o_rd = dc.rd,
 646             o_rs1 = dc.rs1,
 647             o_rs2 = dc.rs2,
 648             o_immediate = dc.immediate,
 649             o_opcode = dc.opcode,
 650             o_decode_action = dc.act
 651         )
 652         self.specials += cd
 653
 654         register_rs1 = Signal(32)
 655         register_rs2 = Signal(32)
 656         self.comb += If(dc.rs1 == 0,
 657                         register_rs1.eq(0)
 658                      ).Else(
 659                         register_rs1.eq(self.registers[dc.rs1-1]))
 660         self.comb += If(dc.rs2 == 0,
 661                         register_rs2.eq(0)
 662                      ).Else(
 663                         register_rs2.eq(self.registers[dc.rs2-1]))
 664
 665         load_store_address = Signal(32)
 666         load_store_address_low_2 = Signal(2)
 667
 668         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 669         self.comb += load_store_address_low_2.eq(
 670                             dc.immediate[:2] + register_rs1[:2])
 671
 672         load_store_misaligned = Signal()
 673
 674         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 675                                      load_store_address_low_2)
 676         self.comb += lsa
 677
 678         # XXX rwaddr not 31:2 any more
 679         self.comb += mi.rw_address.eq(load_store_address[2:])
 680
 681         unshifted_load_store_byte_mask = Signal(4)
 682
 683         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 684
 685         # XXX yuck.  this will cause migen simulation to fail
 686         # (however conversion to verilog works)
 687         self.comb += mi.rw_byte_mask.eq(
 688                 _Operator("<<", [unshifted_load_store_byte_mask,
 689                                         load_store_address_low_2]))
 690
 691         # XXX not obvious
 692         b3 = Mux(load_store_address_low_2[1],
 693                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 694                                                   register_rs2[8:16]),
 695                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 696                                                   register_rs2[24:32]))
 697         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 698                                               register_rs2[16:24])
 699         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 700                                               register_rs2[8:16])
 701         b0 = register_rs2[0:8]
 702
 703         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 704
 705         # XXX not obvious
 706         unmasked_loaded_value = Signal(32)
 707
 708         b0 = Mux(load_store_address_low_2[1],
 709                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 710                                                   mi.rw_data_out[16:24]),
 711                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 712                                                   mi.rw_data_out[0:8]))
 713         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 714                                               mi.rw_data_out[8:16])
 715         b23 = mi.rw_data_out[16:32]
 716
 717         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 718
 719         # XXX not obvious
 720         loaded_value = Signal(32)
 721
 722         b0 = unmasked_loaded_value[0:8]
 723         b1 = Mux(dc.funct3[0:2] == 0,
 724                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 725                 unmasked_loaded_value[8:16])
 726         b2 = Mux(dc.funct3[1] == 0,
 727                 Replicate(~dc.funct3[2] &
 728                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 729                                                   unmasked_loaded_value[7]),
 730                           16),
 731                 unmasked_loaded_value[16:32])
 732
 733         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 734
 735         self.comb += mi.rw_active.eq(~self.reset
 736                         & (ft.output_state == FOS.valid)
 737                         & ~load_store_misaligned
 738                         & ((dc.act & (DA.load | DA.store)) != 0))
 739
 740         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 741
 742         # alu
 743         alu_a = Signal(32)
 744         alu_b = Signal(32)
 745         alu_result = Signal(32)
 746
 747         self.comb += alu_a.eq(register_rs1)
 748         self.comb += alu_b.eq(Mux(dc.opcode[5],
 749                                   register_rs2,
 750                                   dc.immediate))
 751
 752         ali = Instance("cpu_alu", name="alu",
 753             i_funct7 = dc.funct7,
 754             i_funct3 = dc.funct3,
 755             i_opcode = dc.opcode,
 756             i_a = alu_a,
 757             i_b = alu_b,
 758             o_result = alu_result
 759         )
 760         self.specials += ali
 761
 762         lui_auipc_result = Signal(32)
 763         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 764                                              dc.immediate,
 765                                              dc.immediate + ft.output_pc))
 766
 767         self.comb += ft.target_pc.eq(Cat(0,
 768                     Mux(dc.opcode != OP.jalr,
 769                                 ft.output_pc[1:32],
 770                                 register_rs1[1:32] + dc.immediate[1:32])))
 771
 772         misaligned_jump_target = Signal()
 773         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 774
 775         branch_arg_a = Signal(32)
 776         branch_arg_b = Signal(32)
 777         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 778                                           register_rs1[31] ^ ~dc.funct3[1]))
 779         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 780                                           register_rs2[31] ^ ~dc.funct3[1]))
 781
 782         branch_taken = Signal()
 783         self.comb += branch_taken.eq(dc.funct3[0] ^
 784                                      Mux(dc.funct3[2],
 785                                          branch_arg_a < branch_arg_b,
 786                                          branch_arg_a == branch_arg_b))
 787
 788         m = M(self.comb, self.sync)
 789         mstatus = MStatus(self.comb, self.sync)
 790         mie = MIE(self.comb, self.sync)
 791         misa = Misa(self.comb, self.sync)
 792         mip = MIP(self.comb, self.sync)
 793
 794         # CSR decoding
 795         csr = CSR(self.comb, self.sync, dc, register_rs1)
 796
 797         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 798                                  branch_taken, misaligned_jump_target,
 799                                  csr.op_is_valid)
 800
 801         minfo = MInfo(self.comb)
 802
 803         self.sync += If(~self.reset,
 804                         self.main_block(minfo, csr, mi, m, mstatus, ft, dc,
 805                                         load_store_misaligned,
 806                                         loaded_value,
 807                                        alu_result,
 808                                        lui_auipc_result)
 809                      )
 810
 811 if __name__ == "__main__":
 812     example = CPU()
 813     print(verilog.convert(example,
 814          {
 815            example.tty_write,
 816            example.tty_write_data,
 817            example.tty_write_busy,
 818            example.switch_2,
 819            example.switch_3,
 820            example.led_1,
 821            example.led_3,
 822            }))
 823
 824 """
 825
 826     always @(posedge clk) begin:main_block
 827         if(reset) begin
 828             reset_to_initial();
 829             disable main_block;
 830         end
 831         case(fetch_output_state)
 832         `fetch_output_state_empty: begin
 833         end
 834         `fetch_output_state_trap: begin
 835             handle_trap();
 836         end
 837         `fetch_output_state_valid: begin:valid
 838             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 839                 handle_trap();
 840             end
 841             else if((decode_action & `decode_action_load) != 0) begin
 842                 if(~memory_interface_rw_wait)
 843                     write_register(decoder_rd, loaded_value);
 844             end
 845             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 846                 write_register(decoder_rd, alu_result);
 847             end
 848             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 849                 write_register(decoder_rd, lui_auipc_result);
 850             end
 851             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 852                 write_register(decoder_rd, fetch_output_pc + 4);
 853             end
 854             else if((decode_action & `decode_action_csr) != 0) begin:csr
 855                 reg [31:0] csr_output_value;
 856                 reg [31:0] csr_written_value;
 857                 csr_output_value = 32'hXXXXXXXX;
 858                 csr_written_value = 32'hXXXXXXXX;
 859                 case(csr_number)
 860                 `csr_cycle: begin
 861                     csr_output_value = cycle_counter[31:0];
 862                 end
 863                 `csr_time: begin
 864                     csr_output_value = time_counter[31:0];
 865                 end
 866                 `csr_instret: begin
 867                     csr_output_value = instret_counter[31:0];
 868                 end
 869                 `csr_cycleh: begin
 870                     csr_output_value = cycle_counter[63:32];
 871                 end
 872                 `csr_timeh: begin
 873                     csr_output_value = time_counter[63:32];
 874                 end
 875                 `csr_instreth: begin
 876                     csr_output_value = instret_counter[63:32];
 877                 end
 878                 `csr_mvendorid: begin
 879                     csr_output_value = mvendorid;
 880                 end
 881                 `csr_marchid: begin
 882                     csr_output_value = marchid;
 883                 end
 884                 `csr_mimpid: begin
 885                     csr_output_value = mimpid;
 886                 end
 887                 `csr_mhartid: begin
 888                     csr_output_value = mhartid;
 889                 end
 890                 `csr_misa: begin
 891                     csr_output_value = misa;
 892                 end
 893                 `csr_mstatus: begin
 894                     csr_output_value = make_mstatus(mstatus_tsr,
 895                                                     mstatus_tw,
 896                                                     mstatus_tvm,
 897                                                     mstatus_mxr,
 898                                                     mstatus_sum,
 899                                                     mstatus_mprv,
 900                                                     mstatus_xs,
 901                                                     mstatus_fs,
 902                                                     mstatus_mpp,
 903                                                     mstatus_spp,
 904                                                     mstatus_mpie,
 905                                                     mstatus_spie,
 906                                                     mstatus_upie,
 907                                                     mstatus_mie,
 908                                                     mstatus_sie,
 909                                                     mstatus_uie);
 910                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 911                     if(csr_writes) begin
 912                         mstatus_mpie = csr_written_value[7];
 913                         mstatus_mie = csr_written_value[3];
 914                     end
 915                 end
 916                 `csr_mie: begin
 917                     csr_output_value = 0;
 918                     csr_output_value[11] = mie_meie;
 919                     csr_output_value[9] = mie_seie;
 920                     csr_output_value[8] = mie_ueie;
 921                     csr_output_value[7] = mie_mtie;
 922                     csr_output_value[5] = mie_stie;
 923                     csr_output_value[4] = mie_utie;
 924                     csr_output_value[3] = mie_msie;
 925                     csr_output_value[1] = mie_ssie;
 926                     csr_output_value[0] = mie_usie;
 927                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 928                     if(csr_writes) begin
 929                         mie_meie = csr_written_value[11];
 930                         mie_mtie = csr_written_value[7];
 931                         mie_msie = csr_written_value[3];
 932                     end
 933                 end
 934                 `csr_mtvec: begin
 935                     csr_output_value = mtvec;
 936                 end
 937                 `csr_mscratch: begin
 938                     csr_output_value = mscratch;
 939                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 940                     if(csr_writes)
 941                         mscratch = csr_written_value;
 942                 end
 943                 `csr_mepc: begin
 944                     csr_output_value = mepc;
 945                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 946                     if(csr_writes)
 947                         mepc = csr_written_value;
 948                 end
 949                 `csr_mcause: begin
 950                     csr_output_value = mcause;
 951                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 952                     if(csr_writes)
 953                         mcause = csr_written_value;
 954                 end
 955                 `csr_mip: begin
 956                     csr_output_value = 0;
 957                     csr_output_value[11] = mip_meip;
 958                     csr_output_value[9] = mip_seip;
 959                     csr_output_value[8] = mip_ueip;
 960                     csr_output_value[7] = mip_mtip;
 961                     csr_output_value[5] = mip_stip;
 962                     csr_output_value[4] = mip_utip;
 963                     csr_output_value[3] = mip_msip;
 964                     csr_output_value[1] = mip_ssip;
 965                     csr_output_value[0] = mip_usip;
 966                 end
 967                 endcase
 968                 if(csr_reads)
 969                     write_register(decoder_rd, csr_output_value);
 970             end
 971             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 972                 // do nothing
 973             end
 974         end
 975         endcase
 976     end
 977
 978 endmodule
 979 """
 980