add clock domains doc to README
[rv32.git] / cpu.py
2018-11-26 Luke Kenneth Casso... start adding csrs
2018-11-26 Luke Kenneth Casso... move stuff to MInfo
2018-11-26 Luke Kenneth Casso... split CSR to separate class
2018-11-26 Luke Kenneth Casso... add handle_main
2018-11-26 Luke Kenneth Casso... add counters (TODO)
2018-11-26 Luke Kenneth Casso... add csr_is_valid
2018-11-26 Luke Kenneth Casso... start on csr op valid
2018-11-26 Luke Kenneth Casso... CSR decoding
2018-11-26 Luke Kenneth Casso... add handle_trap
2018-11-26 Luke Kenneth Casso... add handle_trap
2018-11-26 Luke Kenneth Casso... add handle trap
2018-11-26 Luke Kenneth Casso... complete get_fetch_action, move to class Fetch
2018-11-26 Luke Kenneth Casso... start converting get_fetch_action
2018-11-26 Luke Kenneth Casso... create Fetch class
2018-11-26 Luke Kenneth Casso... add get_fetch_action ready for conversion
2018-11-25 Luke Kenneth Casso... add mstatus, mip and vendor/arch/mimpl
2018-11-25 Luke Kenneth Casso... add MISA and MIE
2018-11-25 Luke Kenneth Casso... add more logic and mstatus
2018-11-25 Luke Kenneth Casso... calculate lui_auipc
2018-11-25 Luke Kenneth Casso... minor reorg, add alu
2018-11-25 Luke Kenneth Casso... minor reorg, add alu
2018-11-25 Luke Kenneth Casso... convert loaded value
2018-11-25 Luke Kenneth Casso... load value
2018-11-25 Luke Kenneth Casso... more cpu logic
2018-11-25 Luke Kenneth Casso... small cpu reorg
2018-11-25 Luke Kenneth Casso... add load/store misaligned
2018-11-25 Luke Kenneth Casso... add CPU decoder instance
2018-11-25 Luke Kenneth Casso... add cpuFetchStage instance
2018-11-25 Luke Kenneth Casso... adding call out to cpu_memory_interface verilog module...
2018-11-24 Luke Kenneth Casso... stub cpu.py