regfile.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31
  32 class RegFile(Module):
  33
  34     def __init__(self):
  35         Module.__init__(self)
  36         l = []
  37         for i in range(31):
  38             r = Signal(32, name="register%d" % i)
  39             l.append(r)
  40             self.sync += r.eq(Constant(0, 32))
  41         self.registers = Array(l)
  42
  43         self.ra_en = Signal() # read porta enable
  44         self.rb_en = Signal() # read portb enable
  45         self.w_en = Signal()  # write enable
  46         self.read_a = Signal(32) # result porta read
  47         self.read_b = Signal(32) # result portb read
  48         self.writeval = Signal(32) # value to write
  49         self.rs_a = Signal(5) # register port a to read
  50         self.rs_b = Signal(5) # register port b to read
  51         self.rd = Signal(5) # register to write
  52
  53         self.sync += If(self.ra_en,
  54                         self.read(self.rs_a, self.read_a)
  55                      )
  56         self.sync += If(self.rb_en,
  57                         self.read(self.rs_b, self.read_b)
  58                      )
  59         self.sync += If(self.w_en,
  60                         self.write_register(self.rd, self.writeval)
  61                      )
  62
  63     def read(self, regnum, dest):
  64         """ sets the destination register argument
  65             regnum =  0, dest = 0
  66             regnum != 0, dest = regs[regnum-1]
  67         """
  68         return If(regnum == Constant(0, 5),
  69                    dest.eq(Constant(0, 32))
  70                ).Else(
  71                    dest.eq(self.registers[regnum-1])
  72                )
  73
  74     def write_register(self, regnum, value):
  75         """ writes to the register file if the regnum is not zero
  76         """
  77         return If(regnum != 0,
  78                   self.registers[regnum].eq(value)
  79                )
  80
  81 if __name__ == "__main__":
  82     example = RegFile()
  83     print(verilog.convert(example,
  84          {
  85            example.ra_en,
  86            example.rb_en,
  87            example.w_en,
  88            example.read_a,
  89            example.read_b,
  90            example.writeval,
  91            example.rs_a,
  92            example.rs_b,
  93            example.rd,
  94            }))
  95