reorg case statement

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index f35e68c447c491032cc05b2ae0804450c0d4322a..216aa5ef1e3e862a6708c96229173b82bdf6cb41 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -71,28 +71,29 @@ class CPUFetchStage(Module):
 
         self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
 
 
         self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
 

-        fc = {}
-        self.comb += Case(fetch_action, fc)
-        fc[fetch_action_ack_trap] =
+        fc = {
+            fetch_action_ack_trap:

                 If(memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
                     output_state.eq(fetch_output_state_valid)]
                 ).Else(
                    [fetch_pc.eq(mtvec),
                     output_state.eq(fetch_output_state_trap)]
                 If(memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
                     output_state.eq(fetch_output_state_valid)]
                 ).Else(
                    [fetch_pc.eq(mtvec),
                     output_state.eq(fetch_output_state_trap)]

-                )
-        fc[fetch_action_default] = fc[fetch_action_ack_trap]
-        fc[fetch_action_fence] =
+                ),
+            fetch_action_fence:

                 [ fetch_pc.eq(output_pc + 4),
                 [ fetch_pc.eq(output_pc + 4),

-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_jump] =
+                  output_state.eq(fetch_output_state_empty)],
+            fetch_action_jump:

                 [ fetch_pc.eq(target_pc),
                 [ fetch_pc.eq(target_pc),

-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_error_trap] =
+                  output_state.eq(fetch_output_state_empty)],
+            fetch_action_error_trap,

                    [fetch_pc.eq(mtvec),
                    [fetch_pc.eq(mtvec),

-                    output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        fc[fetch_action_wait] =
+                    output_state.eq(fetch_output_state_empty)],
+            fetch_action_wait:

                    [fetch_pc.eq(fetch_pc),
                     output_state.eq(fetch_output_state_valid)]
                    [fetch_pc.eq(fetch_pc),
                     output_state.eq(fetch_output_state_valid)]

+        }
+        fc[fetch_action_default] = fc[fetch_action_ack_trap]
+        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+        self.comb += Case(fetch_action, fc).makedefault(fetch_action_default)