also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
python3 src/soc/litex/florent/sim.py --cpu=libresoc \
--variant=standardjtagtestgpio
+ls180_verilog:
+ python3 src/soc/simple/issuer_verilog.py \
+ --debug=jtag --enable-core --enable-pll \
+ --enable-xics --enable-sram4x4kblock
+ src/soc/litex/florent/libresoc/libresoc.v
+
test: install
python3 setup.py test # could just run nosetest3...
test: install
python3 setup.py test # could just run nosetest3...
cp build/ls180/gateware/mem_1.init .
cp build/ls180/gateware/mem_2.init .
cp build/ls180/gateware/mem_3.init .
cp build/ls180/gateware/mem_1.init .
cp build/ls180/gateware/mem_2.init .
cp build/ls180/gateware/mem_3.init .
+ cp build/ls180/gateware/mem_4.init .
cp libresoc/libresoc.v .
yosys -p 'read_verilog libresoc.v' \
-p 'write_ilang libresoc_cvt.il'
cp libresoc/libresoc.v .
yosys -p 'read_verilog libresoc.v' \
-p 'write_ilang libresoc_cvt.il'
if jtag_en:
self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
if jtag_en:
self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
+ if "sram4k" in variant or variant == 'ls180':
+ self.srams = srams = []
+ for i in range(4):
+ srams.append(wb.Interface(data_width=64, adr_width=29))
+
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
if jtag_en:
self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
if jtag_en:
self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+ if "sram4k" in variant or variant == 'ls180':
+ for i, sram in enumerate(srams):
+ self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+
# and set ibus advanced tags to zero (disable)
self.cpu_params['i_ibus__cti'] = 0
self.cpu_params['i_ibus__bte'] = 0
# and set ibus advanced tags to zero (disable)
self.cpu_params['i_ibus__cti'] = 0
self.cpu_params['i_ibus__bte'] = 0
self.mem_map["main_ram"] = 0x90000000
self.mem_map["sram"] = 0x00000000
self.mem_map["main_ram"] = 0x90000000
self.mem_map["sram"] = 0x00000000
- self.mem_map["sram1"] = 0x00001000
- self.mem_map["sram2"] = 0x00002000
- self.mem_map["sram3"] = 0x00003000
+ self.mem_map["sram1"] = 0x00000200
+ self.mem_map["sram2"] = 0x00000400
+ self.mem_map["sram3"] = 0x00000600
+ self.mem_map["sram4"] = 0x00000800
+ self.mem_map["sram4k_0"] = 0x00001000
+ self.mem_map["sram4k_1"] = 0x00002000
+ self.mem_map["sram4k_2"] = 0x00003000
+ self.mem_map["sram4k_3"] = 0x00004000
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
)
self.platform.name = "ls180"
)
self.platform.name = "ls180"
- # add 3 more 4k integrated SRAMs
+ # add 4 more 4k integrated SRAMs
self.add_ram("sram1", self.mem_map["sram1"], 0x200)
self.add_ram("sram2", self.mem_map["sram2"], 0x200)
self.add_ram("sram3", self.mem_map["sram3"], 0x200)
self.add_ram("sram1", self.mem_map["sram1"], 0x200)
self.add_ram("sram2", self.mem_map["sram2"], 0x200)
self.add_ram("sram3", self.mem_map["sram3"], 0x200)
+ self.add_ram("sram4", self.mem_map["sram4"], 0x200)
# SDR SDRAM ----------------------------------------------
if False: # not self.integrated_main_ram_size:
# SDR SDRAM ----------------------------------------------
if False: # not self.integrated_main_ram_size:
ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+ # add 4x 4k SRAMs
+ for i, sram_wb in enumerate(self.cpu.srams):
+ name = 'sram4k_%d' % i
+ sram_adr = self.mem_map[name]
+ ics_region = SoCRegion(origin=sram_adr, size=0x1000)
+ self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
+
# CRG -----------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
platform.request("sys_rst"))
# CRG -----------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
platform.request("sys_rst"))