soc.git
2021-03-24 Luke Kenneth... add --disable-svp64 to litex sim build
2021-03-23 Tobias Platenmake addrshift human readable
2021-03-23 Tobias Platenadd addrshift function (based on microwatt)
2021-03-22 Luke Kenneth... do not set sv_changed
2021-03-22 Tobias Platentestcase for _get_pgtable_addr
2021-03-22 Luke Kenneth... read predicate mask from correct point in SVP64Asm
2021-03-22 Luke Kenneth... add SVP64Asm option for "m=" to set both src and dest...
2021-03-22 Luke Kenneth... add very small dff sram variant (no 4k SRAMs)
2021-03-22 Cesar StraussAdd test cases for integer VCOMPRESS and VEXPAND
2021-03-22 Luke Kenneth... make sure non-svp64-mode works
2021-03-22 Luke Kenneth... have get_predint return indicator that mask is all 1s
2021-03-22 Cesar StraussSkip fetching integer predicate mask when register...
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding
2021-03-22 Cesar StraussDecode and fetch integer predicate registers
2021-03-21 Cesar StraussFix typo
2021-03-21 Cesar StraussAdd unique name to decoded predication signals
2021-03-21 Cesar StraussRevert removal of *.value from Enums
2021-03-21 Cesar StraussFix syntax
2021-03-21 Luke Kenneth... more TODO comments
2021-03-21 Luke Kenneth... add for-loop pseudocode for CR predicate mask reading
2021-03-21 Luke Kenneth... code comments in TestIssuer
2021-03-21 Luke Kenneth... adjust syntax of SVP64 predicate test cas
2021-03-21 Luke Kenneth... naah. back to "sv." syntax for SVP64 assembly
2021-03-21 Cesar StraussStart work on the predicate fetch FSM
2021-03-21 Cesar StraussAdd predication test case, initially disabled
2021-03-21 Luke Kenneth... add override for build commands powerpc64-linux-gnu...
2021-03-21 Luke Kenneth... enable -mregnames in assembly syntax for unit tests
2021-03-20 Luke Kenneth... more pseudocode in TestIssuer
2021-03-20 Luke Kenneth... move radixmmu to unit test format
2021-03-20 Luke Kenneth... add harmless code and commented-out pseudocode for...
2021-03-20 Luke Kenneth... sort out predicate zeroing in ISACaller
2021-03-20 Luke Kenneth... attempting to add src/dest-zeroing to ISACaller
2021-03-19 Luke Kenneth... more comments for TestIssuer when adding predication
2021-03-19 Tobias Platentestcase for _get_pgtable_addr
2021-03-19 Luke Kenneth... decode predicate src/dest zeroing in SVP64RMModeDecode
2021-03-19 Luke Kenneth... comments for TestIssuer get_predint and get_predcr
2021-03-19 Luke Kenneth... add more pieces of predication reading puzzle to TestIssuer
2021-03-19 Luke Kenneth... cleanup TestIssuer (comments)
2021-03-19 Luke Kenneth... spelling
2021-03-19 Luke Kenneth... code-shuffle in TestIssuer, split out setting up periph...
2021-03-19 Luke Kenneth... move duplicated code to a function in TestIssuer
2021-03-18 Luke Kenneth... more hint/comments
2021-03-18 Luke Kenneth... comments / code-shuffle
2021-03-18 Luke Kenneth... update TestIssuer comments
2021-03-18 Luke Kenneth... add comments on most likely place to put predicate...
2021-03-18 Luke Kenneth... comments TestIssuer, add a stub FSM
2021-03-18 Luke Kenneth... add MSR PR read in RADIXMMU ISACaller
2021-03-18 Luke Kenneth... re-add auto-generated file simplev.py to gitignore
2021-03-18 Jacob Lifshayre-add nmigen-type-annotations with libre-soc url
2021-03-18 Luke Kenneth... experiment in radixmmu with returning addr_next (and...
2021-03-18 Luke Kenneth... add sv_out2 to PowerDecode and PowerDecoder2
2021-03-18 Luke Kenneth... cross-reference to bug #619
2021-03-18 Luke Kenneth... add auto-generation of out2 column in SVP64RM
2021-03-18 Luke Kenneth... remove nmigen-type-annotations temporarily
2021-03-18 Luke Kenneth... remove nmigen-type-annotations temporarily
2021-03-18 Luke Kenneth... add option to move RS in CSV file reading, for compatib...
2021-03-17 Luke Kenneth... correct comments
2021-03-17 Luke Kenneth... re-enable SVP64 ISACaller predicate tests
2021-03-17 Luke Kenneth... add ascii graphic for extsw svp64 operation
2021-03-17 Luke Kenneth... add more explanatory comments
2021-03-17 Luke Kenneth... add twin-predicated extsw SVP64 ISACaller unit test
2021-03-17 Luke Kenneth... add SVP64 dststep incrementing in PowerDecoder2, Testis...
2021-03-17 Luke Kenneth... add CR-based predication to ISACaller
2021-03-17 Tobias Platencleanup raduxmmu._walk_tree
2021-03-17 Tobias Platencreate iterative mmu lookup loop
2021-03-17 Luke Kenneth... add SVP64 INT-style predication to ISACaller
2021-03-17 Luke Kenneth... add predication SVP64 unit test
2021-03-17 Luke Kenneth... add predication read ports (CR and INT)
2021-03-17 Luke Kenneth... whoops shift has to be done at same bitwidth
2021-03-17 Luke Kenneth... split out new_lookup function
2021-03-17 Luke Kenneth... link up SVP64 RM Mode decoding into PowerDecoder2
2021-03-17 Luke Kenneth... add priv and mode to RADIXMMU
2021-03-17 Luke Kenneth... add instr_fetch mode to ISACaller Mem and RADIXMMU
2021-03-17 Luke Kenneth... whitespace
2021-03-17 Luke Kenneth... add in SVP64 RM Mode decoder
2021-03-16 Tobias Platenradixmmu: detect badtree
2021-03-16 Tobias Platenadd valid, leaf to loop
2021-03-16 Cesar StraussUse symbolic values for subfields and bits
2021-03-16 Cesar StraussAdd subfield and bit definitions for the SVP64 RM mode...
2021-03-16 Cesar StraussDefine and initialise the mode variable, to be used...
2021-03-16 Cesar StraussRename class so it does not clash with the enum
2021-03-15 Cesar StraussFix import
2021-03-15 Tobias Platenadd rpte bitfields valid and leaf
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-14 Cesar StraussActivate the VL==0 loop with any SVP64 prefix whatsoever
2021-03-13 Luke Kenneth... add setvl unit test assertions, add 2nd test
2021-03-13 Luke Kenneth... get first revision setvl operational in ISACaller
2021-03-13 Luke Kenneth... add setvl-to-long converter in SVP64Asm (sigh)
2021-03-13 Luke Kenneth... add setvl unit test
2021-03-13 Luke Kenneth... update submodule to include simplev setvl
2021-03-13 Luke Kenneth... include SVSTATE in namespace, passing to ISACaller
2021-03-12 Jacob Lifshayupdate submodule
2021-03-12 Jacob Lifshayadd setvl to decoder
2021-03-12 Jacob Lifshayautoformat code
2021-03-12 Luke Kenneth... add OP_SETVL to MicrOp in power_enums.py
2021-03-12 Luke Kenneth... add ability to set and distinguish RT=0 (RT_OR_ZERO...
2021-03-12 Luke Kenneth... use PowerDecoder2.loop_continue instead of no_out_vec
2021-03-12 Luke Kenneth... remove old code
2021-03-12 Luke Kenneth... remove old code
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