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Change DCSR bits to match spec.
[riscv-isa-sim.git]
/
debug_rom
/
debug_rom.h
2016-05-23
Tim Newsome
Change DCSR bits to match spec.
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2016-05-23
Tim Newsome
Use fence.i in Debug ROM.
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2016-05-23
Tim Newsome
Add dret.
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2016-05-23
Tim Newsome
Implement single memory read access.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode, stay in Debug Mode.
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2016-05-23
Tim Newsome
Have Debug memory kind of working again.
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2016-05-23
Tim Newsome
Fix race using fence.
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2016-05-23
Tim Newsome
processor_t unfriends gdbserver_t.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
Jump to the correct (temporary) Debug RAM address.
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2016-05-23
Tim Newsome
Clean up how Debug ROM is included.
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