git.libre-soc.org Git - riscv-isa-sim.git/history

2011-04-12	Andrew Waterman	[sim,pk] fixed minor pk bugs and trap codes	blob \| commitdiff \| raw
2011-04-12	Andrew Waterman	[xcc,sim,opcodes] more rvc instructions and bug fixes	blob \| commitdiff \| raw \| diff to current
2011-04-10	Andrew Waterman	[xcc, sim] added rvc insn c.li; misc fixes	blob \| commitdiff \| raw \| diff to current
2011-04-10	Andrew Waterman	[xcc,pk,sim,opcodes] added first RVC instruction	blob \| commitdiff \| raw \| diff to current
2010-10-05	Andrew Waterman	[xcc,sim] eliminated vectored traps	blob \| commitdiff \| raw \| diff to current
2010-09-11	Andrew Waterman	[sim, pk] cleaned up exception vectors and FP exc flags	blob \| commitdiff \| raw \| diff to current
2010-07-29	Andrew Waterman	[sim,xcc] Changed instruction format to RISC-V	blob \| commitdiff \| raw \| diff to current
2010-07-19	Andrew Waterman	Reorganized directory structure	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike