radixmmu: handle badtree
[soc.git] / src / soc / decoder /
2021-04-14 Tobias Platenradixmmu: handle badtree
2021-04-14 Tobias Platenupdate test case for radix mmu
2021-04-14 Tobias Platenradixmmu: error handling
2021-04-13 Tobias Platenmore fixes for radixmmu.py
2021-04-13 Tobias Platenfix AttributeError in radixmmu testcase
2021-04-12 Tobias Platenradixmmu.py: cleanup
2021-04-11 Tobias Platenfix bug in radixmmu.py
2021-04-11 Tobias Platenradixmmu: more work on segment check
2021-04-10 Cesar StraussAdd test cases for 1<<r3 predication
2021-04-07 Tobias PlatenWIP: calculate address of first page table entry
2021-04-07 Tobias Platenradixmmu: fix segment_check function and its caller
2021-04-06 Cesar StraussStart the test case from a point where the predicate...
2021-04-04 Cesar StraussAdd test case for reentrant VL loop
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd twin predication test
2021-04-02 Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussAdd VEXPAND test case for the ISA Simulator
2021-04-02 Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
2021-04-02 Cesar StraussDisallow dm=xx on single predication
2021-03-31 Tobias Platen_new_lookup: remove unused argument mbits
2021-03-31 Tobias Platenradixmmu: read prtable entry
2021-03-31 Tobias Platenradixmmu.py: remove redunant code
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platenmore work on _prtable_lookup and testcase
2021-03-30 Luke Kenneth Casso... add comments
2021-03-30 Luke Kenneth Casso... use PRTBL SPR in RADIXMMU
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platencomment about microwatt implementation details
2021-03-30 Luke Kenneth Casso... add comments, correct load addresses
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Alain D D WilliamsAllow comments
2021-03-30 Tobias Platenadd function _prtable_lookup and unit test
2021-03-30 Luke Kenneth Casso... might have RADIXMMU at least semi-working... maybe
2021-03-30 Luke Kenneth Casso... use assertEqual in RADIXMMU unit test
2021-03-29 Luke Kenneth Casso... correct segment check (off by one in LE/BE convert
2021-03-29 Luke Kenneth Casso... sort out pywriter.py when run with no args
2021-03-28 Luke Kenneth Casso... whoops spelling mistake in SPRreduced Enums
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-25 Tobias Platenradixmmu.py: cleanup, documentation
2021-03-25 Tobias Platenfix _get_prtable_addr, cleanup
2021-03-24 Luke Kenneth Casso... debug output
2021-03-24 Luke Kenneth Casso... add comment skipping in pagereader.py
2021-03-24 Luke Kenneth Casso... make svp64 isa caller unit tests more obvious
2021-03-24 Luke Kenneth Casso... add option to stop writing isa all.py in pseudocode...
2021-03-24 Luke Kenneth Casso... fix nonzero test in ISACaller RADIXMMU
2021-03-23 Tobias Platenmake addrshift human readable
2021-03-23 Tobias Platenadd addrshift function (based on microwatt)
2021-03-22 Luke Kenneth Casso... do not set sv_changed
2021-03-22 Tobias Platentestcase for _get_pgtable_addr
2021-03-22 Luke Kenneth Casso... read predicate mask from correct point in SVP64Asm
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-20 Luke Kenneth Casso... move radixmmu to unit test format
2021-03-20 Luke Kenneth Casso... sort out predicate zeroing in ISACaller
2021-03-20 Luke Kenneth Casso... attempting to add src/dest-zeroing to ISACaller
2021-03-19 Tobias Platentestcase for _get_pgtable_addr
2021-03-19 Luke Kenneth Casso... decode predicate src/dest zeroing in SVP64RMModeDecode
2021-03-18 Luke Kenneth Casso... comments / code-shuffle
2021-03-18 Luke Kenneth Casso... add MSR PR read in RADIXMMU ISACaller
2021-03-18 Luke Kenneth Casso... re-add auto-generated file simplev.py to gitignore
2021-03-18 Luke Kenneth Casso... experiment in radixmmu with returning addr_next (and...
2021-03-18 Luke Kenneth Casso... add sv_out2 to PowerDecode and PowerDecoder2
2021-03-18 Luke Kenneth Casso... cross-reference to bug #619
2021-03-18 Luke Kenneth Casso... add auto-generation of out2 column in SVP64RM
2021-03-18 Luke Kenneth Casso... add option to move RS in CSV file reading, for compatib...
2021-03-17 Luke Kenneth Casso... correct comments
2021-03-17 Luke Kenneth Casso... re-enable SVP64 ISACaller predicate tests
2021-03-17 Luke Kenneth Casso... add ascii graphic for extsw svp64 operation
2021-03-17 Luke Kenneth Casso... add more explanatory comments
2021-03-17 Luke Kenneth Casso... add twin-predicated extsw SVP64 ISACaller unit test
2021-03-17 Luke Kenneth Casso... add SVP64 dststep incrementing in PowerDecoder2, Testis...
2021-03-17 Luke Kenneth Casso... add CR-based predication to ISACaller
2021-03-17 Tobias Platencleanup raduxmmu._walk_tree
2021-03-17 Tobias Platencreate iterative mmu lookup loop
2021-03-17 Luke Kenneth Casso... add SVP64 INT-style predication to ISACaller
2021-03-17 Luke Kenneth Casso... add predication SVP64 unit test
2021-03-17 Luke Kenneth Casso... whoops shift has to be done at same bitwidth
2021-03-17 Luke Kenneth Casso... split out new_lookup function
2021-03-17 Luke Kenneth Casso... link up SVP64 RM Mode decoding into PowerDecoder2
2021-03-17 Luke Kenneth Casso... add priv and mode to RADIXMMU
2021-03-17 Luke Kenneth Casso... add instr_fetch mode to ISACaller Mem and RADIXMMU
2021-03-17 Luke Kenneth Casso... whitespace
2021-03-17 Luke Kenneth Casso... add in SVP64 RM Mode decoder
2021-03-16 Tobias Platenradixmmu: detect badtree
2021-03-16 Tobias Platenadd valid, leaf to loop
2021-03-16 Cesar StraussUse symbolic values for subfields and bits
2021-03-16 Cesar StraussDefine and initialise the mode variable, to be used...
2021-03-16 Cesar StraussRename class so it does not clash with the enum
2021-03-15 Cesar StraussFix import
2021-03-15 Tobias Platenadd rpte bitfields valid and leaf
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-13 Luke Kenneth Casso... add setvl unit test assertions, add 2nd test
2021-03-13 Luke Kenneth Casso... get first revision setvl operational in ISACaller
2021-03-13 Luke Kenneth Casso... add setvl unit test
2021-03-13 Luke Kenneth Casso... include SVSTATE in namespace, passing to ISACaller
2021-03-12 Jacob Lifshayadd setvl to decoder
2021-03-12 Jacob Lifshayautoformat code
2021-03-12 Luke Kenneth Casso... add OP_SETVL to MicrOp in power_enums.py
2021-03-12 Luke Kenneth Casso... add ability to set and distinguish RT=0 (RT_OR_ZERO...
2021-03-12 Luke Kenneth Casso... add more sophisticated checking of whether SVP64 loop...
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