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add random dcache mem test
2020-09-12 Luke Kenneth Casson... add random dcache mem test
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2020-09-12 Luke Kenneth Casson... cache valid corrupted: fixed
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2020-09-12 Luke Kenneth Casson... adding names to array signals
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2020-09-12 Luke Kenneth Casson... whoops, indentation error
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2020-09-12 Luke Kenneth Casson... enable Display debugs
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2020-09-12 Luke Kenneth Casson... set bytesel in dcache store
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2020-09-11 Luke Kenneth Casson... separat stbs_done into ld/st
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2020-09-11 Luke Kenneth Casson... dcache load/store test
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2020-09-11 Luke Kenneth Casson... debugging dcache
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2020-09-11 Luke Kenneth Casson... wrong width for data / addr
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2020-09-11 Luke Kenneth Casson... connect up WB SRAM to dcache test
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2020-09-11 Luke Kenneth Casson... start on dcache test
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2020-09-11 Luke Kenneth Casson... missing comb +=
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2020-09-11 Luke Kenneth Casson... missing maybe_tlb_plrus
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2020-09-11 Luke Kenneth Casson... WAY_BITS not TLB_WAY_BITS
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2020-09-11 Luke Kenneth Casson... whoops new node not to be calculated at end
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2020-09-11 Luke Kenneth Casson... try to get better DTLBUpdate
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2020-09-11 Luke Kenneth Casson... simplify dcache pending
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2020-09-11 Luke Kenneth Casson... move dcache pending test to separate module
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2020-09-11 Luke Kenneth Casson... more error correction in dcache
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2020-09-11 Luke Kenneth Casson... use module for TLBUpdate
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2020-09-11 Luke Kenneth Casson... add brackets round if & in dcache
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2020-09-10 Luke Kenneth Casson... simplify read/write pte
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2020-09-10 Luke Kenneth Casson... eek, big sort-out of syntax errors in dcache.py, now...
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2020-09-10 Luke Kenneth Casson... starting on dcache syntax errors
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2020-09-10 Luke Kenneth Casson... add PLRU microwatt conversion
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2020-09-10 Luke Kenneth Casson... add function calls to construct dcache
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2020-09-10 Luke Kenneth Casson... correct some errors introduced in dcache.py
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2020-09-10 Luke Kenneth Casson... add docstring for PowerOp class
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2020-09-09 Luke Kenneth Casson... more laborious line-by-line checking of dcache.py conversion
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2020-09-08 Luke Kenneth Casson... add PowerDecoder explanation
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2020-09-08 Luke Kenneth Casson... bit of a mess, trying to get PowerDecode to not create...
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2020-09-08 Luke Kenneth Casson... subset columns for PowerDecoder - bit of a mess (done...
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2020-09-08 Luke Kenneth Casson... create a special subset of Decoder Record for storing...
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2020-09-08 Luke Kenneth Casson... pass in state into PowerDecode2, save on eqs and wires
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2020-09-08 Luke Kenneth Casson... give Decode2Execute1Type in core a name
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2020-09-08 Luke Kenneth Casson... argh, somehow EINT check got moved out of if/elif block
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2020-09-08 Luke Kenneth Casson... capture trap / irq conditions in flags for debug purposes
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2020-09-08 Luke Kenneth Casson... pass in CoreState to PowerDecoder rather than eq a...
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2020-09-08 Luke Kenneth Casson... whoops trap address being set in wrong Decode2ExecuteType...
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2020-09-08 Luke Kenneth Casson... add cxxsim option
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2020-09-07 Luke Kenneth Casson... use PowerDecoderSubsets for FUs, except for TRAP which...
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2020-09-07 Luke Kenneth Casson... add per-FU PowerDecoders. should now be subsettable
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2020-09-07 Luke Kenneth Casson... create eq_from function based on eq_from_execute1
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2020-09-07 Luke Kenneth Casson... debug print statement in eq_from_execute
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2020-09-07 Luke Kenneth Casson... oe_ok renamed to oe, needed in regspec_decode_read
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2020-09-07 Luke Kenneth Casson... add insn and fn_unit to CompLDSTOpSubset
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2020-09-07 Luke Kenneth Casson... add pspec and opsubsetkls to CompUnits
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2020-09-07 Luke Kenneth Casson... make immediate decoding optional on-demand
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2020-09-07 Luke Kenneth Casson... whoops spelling mistake outOut_carry not outPut_carry
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2020-09-07 Luke Kenneth Casson... convert mul test to use Power Decode subset
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2020-09-07 Luke Kenneth Casson... convert shift_rot to subset decoder
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2020-09-07 Luke Kenneth Casson... convert branch test to PowerDecodeSubset form
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2020-09-07 Luke Kenneth Casson... convert CR to PowerDecodeSubset format
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2020-09-07 Luke Kenneth Casson... bit of a big reorg of data structures
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2020-09-07 Luke Kenneth Casson... split out PowerDecode2 into PowerDecodeSubset
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2020-09-07 Luke Kenneth Casson... large stack of moving stuff around in dcache
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2020-09-07 Luke Kenneth Casson... adjust indentation of dcache_slow
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2020-09-07 Luke Kenneth Casson... more dcache translation
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2020-09-07 Luke Kenneth Casson... add start on cache_ram.vhdl to nmigen conversion
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2020-09-07 Luke Kenneth Casson... more dcache translation
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2020-09-07 Luke Kenneth Casson... allow Decode2ToExecute1Type to take an opkls argument
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2020-09-07 Luke Kenneth Casson... whoops truncated the mb and me fields
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2020-09-07 Luke Kenneth Casson... minor reorg on PowerDecoder
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2020-09-06 Luke Kenneth Casson... comment, nothing unusual when Trap Type is DEC
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2020-09-06 Luke Kenneth Casson... decoder immediate b split out to DecodeBImm
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2020-09-06 Luke Kenneth Casson... decoder immediate a split out to DecodeAImm
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2020-09-06 Luke Kenneth Casson... add row subset selector for PowerDecode.
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2020-09-06 Luke Kenneth Casson... add row_subset (doesnt do anything yet)
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2020-09-06 Luke Kenneth Casson... pass col_subset throughout PowerDecoder
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2020-09-06 Luke Kenneth Casson... reorganise PowerOp to be dynamic
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2020-09-06 Luke Kenneth Casson... reorg of PowerOp to be able to dynamically subset it
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2020-09-06 Luke Kenneth Casson... grr, autopep8 messing up
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2020-09-06 Luke Kenneth Casson... copy dec SPR into decoder cur_state
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2020-09-06 Luke Kenneth Casson... add reset option to Register
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2020-09-06 Luke Kenneth Casson... wark-wark, fast regs is binary-addressed
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2020-09-06 Luke Kenneth Casson... add unit test for slow SPRs (SPRG0/1)
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2020-09-06 Luke Kenneth Casson... minor code-munge on SPR-to-FAST mapping
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2020-09-06 Luke Kenneth Casson... use with subTest in spr unit test
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2020-09-06 Luke Kenneth Casson... redo generation of microwatt.v from litex
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2020-09-06 Luke Kenneth Casson... add comments for DEC / TB
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2020-09-06 Luke Kenneth Casson... add a DEC/TB FSM to TestIssuer
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2020-09-06 Luke Kenneth Casson... move DEC and TB from StateRegs to FastRegs for several...
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2020-09-06 Luke Kenneth Casson... add DEC SPR to CoreState and PowerDecoder, activate...
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2020-09-06 Luke Kenneth Casson... add DEC and TB to State regfile
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2020-09-06 Luke Kenneth Casson... add DEC/TB SPRs to spr pipeline
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2020-09-05 Luke Kenneth Casson... add comments on MSR read
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2020-09-05 Luke Kenneth Casson... move GPIO IRQ to 15 to match microwatt modifications
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2020-09-05 Luke Kenneth Casson... hmmm XICS data being asserted on wb bus for too long
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2020-09-05 Luke Kenneth Casson... argh missed a VHDL "&" translating to Cat
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2020-09-05 Luke Kenneth Casson... reduce XICS address lookup by 2 bits
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2020-09-05 Luke Kenneth Casson... MSR read in INSN_READ only occurs for 1 cycle
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2020-09-05 Luke Kenneth Casson... sync on ICP eint
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2020-09-05 Luke Kenneth Casson... connect XICS core irq to Decode2 eint
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2020-09-05 Luke Kenneth Casson... whoops, combinatorial loop on pending_priority
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2020-09-05 Luke Kenneth Casson... use stbcix in test
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2020-09-05 Luke Kenneth Casson... XICS addresses in words: divide by 4
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2020-09-05 Luke Kenneth Casson... whoops, ICS in litex sim needs to be 0x1000 size region
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2020-09-05 Luke Kenneth Casson... add lwzcix unit test
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2020-09-05 Luke Kenneth Casson... increase wishbone address width to 29 for xics and...
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